A General and Transformable #Model Platform for Emerging Multi-Gate MOSFETs - IEEE Xplore Document https://t.co/q27OgRX5Fd

A General and Transformable #Model Platform for Emerging Multi-Gate MOSFETs - IEEE Xplore Document https://t.co/q27OgRX5Fd

— Wladek Grabinski (@wladek60) August 14, 2017

from Twitter https://twitter.com/wladek60

August 14, 2017 at 02:01PM
via IFTTT

Mini-Colloquium (MQ) on Nanoelectronics

AGENDA
DATE: Saturday Aug. 26, 2016

VENUE: IIT Kanpur L16

This Mini-Colloquium (MQ) on Nanoelectronics is being hosted by the IEEE Electron Device Society UP Chapter in collaboration with the Department of Electrical Engineering at IIT Kanpur. Distinguished speakers from renowned universities will be presenting on wide range of topics in Nanoelectronics. The MQ will be organized into 1 hour talks by the speakers. The agenda would be as follows:

Time	Topic	Speaker
9:00 - 9:15	Inauguration
9:15 - 9:30	High Tea
9:30 - 10:30	Nanotransistors with 2D materials: Opportunities and Challenges	Prof. Navkanta Bhat IISc
10:30 - 11:30	Revisiting gate C-V characterization for high mobility semiconductor MOS devices	Prof. Anisul Haque East West Univ.
11:30 - 11:45	Tea
11:45 - 12:45		Prof. V. Ramgopal Rao IIT Delhi
12:45 - 14:15	Lunch
14:15 - 15:15	ASM-HEMT - First Industry Standard Compact Model for GaN HEMTs	Prof. Yogesh Singh Chauhan IIT Kanpur
15:15 - 16:15	Spintronics - Perspectives and Challenges	Prof. Brajesh Kumar Kaushik IIT Roorkee
16:15 - 16:30	Tea
16:30 - 17:30	Advanced Hetero structure based Nano Scale MOSFETs	Prof. Chandan Kumar Sarkar Jadavpur Univ.

Coordinator: Dr. Yogesh S.Chauhan IIT Kanpur, India
Website: http://www.iitk.ac.in/nanolab/MQ/index.html

ICCDCS 2017

Tenth International Caribbean Conference on Devices, Circuits and Systems (ICCDCS 2017)

June 5-7 2017, Cozumel, México

08:00 to 9:00	Registration	Registration	Registration
08:45 to 9:00	Opening Ceremony
09:00 to 10:00	Key Note 1: "Adaptive Heterogenous Multi-Core Technologies- Intelligent, Interconnected and Integrated Cyber-Physical Systems (I3CPS)", Jürgen Becker	Key Note 3: "The Life and Times of Eugeni García", Benjamín Íñiguez	Key Note 6: "On the Extraction Methods for MOSFET Series Resistance and Mobility Degradation using a Single Test Device",Adelmo Ortiz Conde
10:00 to 10:30	Break	Break	Break
10:30 to 12:30	Session 1	Session 3	Session 5
10:30 to 10:50	"Model Based Photopic Electroretinogram Source Separation: A Multiresolution Analysis Approach", Prashanth Chetlur Adithya, Alaql Abdulrahman, Radouil Tzekov, Ravi Sankar and Wilfrido Moreno	"A Programmable CMOS Voltage Controlled Ring Oscillator for Radio-Frequency Diathermy On-chip Circuit", Antonio Corres- Matamoros, Esteban Martinez-Guerrero and Jose E. Rayas-Sanchez	"Health Index Assessment for Power Transformers with Thermal Upgraded Paper up to 230kV, Using Fuzzy Inference. Part II: A Sensibility Analysis", Diego Chacón, Juan Pablo Lata and Ricardo Medina
10:50 to 11:10	"Analytical Model Parameter Determination for Microwave On-Chip Inductors up to the Second Resonant Frequency", José Valdés Rayón, Reydezel Torres and Roberto Murphy	"A logarithmic CMOS image sensor with wide output voltage swing range", Fernando Campos, Mário Bordon, Marcelo Silva and Jacobus Swart	"Implementation Model Using a Hippocratic Protocol in Mobile Terminals with NFC Technology", Carlos Kowalevicz, Jose Pirrone Puma and Monica Huerta
11:10 to 11:30	"Energy Consumption Improvement based on Distance Adaptive Modulation in Optical Elastic Network", Sabi Bandiri, Rafael Braga, Tales Pimenta and Danilo Spadoti	"Improving Magnitude Response in Two-Stage Corrector Comb Structure", Gordana Jovanovic Dolecek and Lyda Herrera Sepulveda	"Internet of Things as an Attack Vector to Critical Infrastructures of Cities", Pablo Leonidas Gallegos-Segovia, Jack Fernando M. Larios-Rosillo and Erwin Jairo Sacoto-Cabrera
11:30 to 11:50	"Switching Region Analysis for SOTB Technology", Carlos Cortes Torres, Nobuyuki Yamasaki and Hideharu Amano	"Analysis of the influence of the buffer layer in the characteristic impedance of electro-optic modulators", Ana Gabriela Correa Mena, Luis Alejandro González Mondragón, Leidy Johana Quinteros Rodríguez, José Valdés Rayón and Ignacio Enrique Zaldívar Huerta	"Sensors for Parkinson's Disease Evaluation", Raquel Torres, Monica Huerta, Ricardo Gonzalez, Roger Clotet and Juan Pablo Bermeo
11:50 to 12:10	"Scalable Models to Represent the Via-Pad Capacitance and Via-Traces Inductance in Multilayer PCB High-Speed Interconnects", Abraham Isidoro Muñoz, Miguel Angel Tlaxcalteco Matus, Reydezel Torres Torres and Gaudencio Hernandez Sosa	"Impact of neglecting the metal losses on the extraction of the relative permittivity from PCB transmission line measurements", Erika Yazmin Teran Bahena and Reydezel Torres Torres	"QoS Evaluation of VPN in a Raspberry Pi devices over Wireless Network", Luis Caldas, Juan Jara and Mónica Huerta
12:10 to 12:30	"Implementation of a Reconfigurable Neural Network in FPGA", Janaina Oliveira, Robson Moreno, Odilon Dutra and Tales Pimenta	"Reconfigurable FIR Filter Coefficient Optimization in Post-Silicon Validation to Improve Eye Diagram for Optical Interconnects",Ismael Duron-Rosales, Francisco E. Rangel-Patino, Jose E. Rayas-Sanchez, Jose L. Chavez-Hurtado and Nagib Hakim	"A Proposed Digital Predistorter Based on NLMS and PSO Algorithms", Omar Alngar, Walid El-Deeb and El-Sayed El-Rabaie
12:30 to 15:00	Lunch	Lunch	Closing remarks
15:00 to 16:00	Key Note 2: "Following the Path of 3D Integration", Malgorzata Chrzanowska-Jeske	Key Note 4: “Modeling and Verification of Heterogeneous Systems”, Filipe Vinci
16:00 to 16:15	Break	Poster Introduction*
16:15 to 17:55	Session 2	Session 4
16:15 to 16:35	"MRAM control Transistor Resilience against Heavy-Ion Impacts", Walter Enrique Calienes Bartra, Raphael Brum, Guilherme Flach and Ricardo Reis	Break w/poster session (16:15 to 17:00)
16:35 to 16:55	"A Charge-controlled Memristor Model for Image Edge Detection with a Memristive Grid", Arturo Sarmiento and Yojanes Rodríguez-Velásquez
16:55 to 17:15	"Characterization and modelling of Ag/TiO2/ITO devices exhibiting bipolar memristive properties", Jesús Jiménez-León, Arturo Sarmiento, Carlos De La Cruz Blas and Cristina Gomez-Polo
17:15 to 17:35	"Assessing the accuracy of the open, short and open-short de-embedding methods for on-chip transmission line s-parameters measurements", Juan Garcia Santos and Reydezel Torres	Key Note 5: (17:00 to 18:00) "Innovation by ASIC design and emerging substream markets"Jacobus Swart
17:35 to 17:55	"Evaluation of Interconnects Based on Electromigration Criteria and Circuit Performance", Rafael Nunes, Roberto Orio and Jacobus Swart
19:00	Welcome Cocktail
19:30		Conference Banquet

Poster Session:

"Differentiated synchronization plus FHIR a solution for EMR's Ecosystem", Roger Clotet, Emilio Hernández and Monica Karel Huerta

"Design and Validation of a Portable Radio-Frequency Diathermy Prototype", Antonio Corres-Matamoros, Esteban Martinez-Guerrero and Jose E. Rayas-Sanchez

"Stimulating social interaction among elderly people through sporadic social networks", Jorge Osmani Ordoñez-Ordoñez, Jack Fernando Bravo-Torres, Oscar David Sari-Villa, Esteban Fernando Ordoñez-Morales, Martín López-Nores and Yolanda Blanco-Fernández

"Sensing Climatic Variables in a Orchid Greenhouse", Luis Fernandez, Mónica Huerta, Giovanni Sagbay, Roger Clotet and Angel Soto

"Low cost system for monitoring physiological signals using FPGA and Android Tablet", J. Bucheli, D. Rivas, J. Gavilema, D. Mullo, J. L. Carrillo, M. Huerta

Basics of MOSFET Modeling

Basics of MOSFET Modeling with LabVIEW/LTspice 

• Introduction to MOSFET Models 
• Functions and Parameter Extraction
• visit http://mosfet-engineer.blogspot.com

[paper] On the Physical Behavior of Cryogenic IV and III-V Schottky Barrier MOSFET Devices

On the Physical Behavior of Cryogenic IV and III–V Schottky Barrier MOSFET Devices

Mike Schwarz, Member, IEEE, Laurie E. Calvet, Member, IEEE, John P. Snyder, Member, IEEE, Tillmann Krauss, Udo Schwalke, Senior Member, IEEE, and Alexander Kloes, Senior Member, IEEE

in IEEE TED , vol.PP, no.99, pp.1-8

doi: 10.1109/TED.2017.2726899

Abstract: The physical influence of temperature down to the cryogenic regime is analyzed in a comprehensive study and the comparison of IV and III-V Schottky barrier (SB) double-gate MOSFETs. The exploration is done using the Synopsys TCAD Sentaurus device simulator and first benchmarked with experimental data. The important device physics of both SB-MOSFETs and conventional MOSFETs are reviewed. The impact of temperature on device performance down to the liquid-nitrogen regime is then explored. We find reduced drive currents in SB-MOSFETs fabricated on small effective mass materials and that SB lowering can significantly improve SB-MOSFETs, especially at low temperatures [read more...]

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination

[paper] Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS

T. Komawaki, M. Yabuuchi, R. Kishida, J. Furuta, T. Matsumoto and K. Kobayashi

Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS

2017 IEEE ICICDT, Austin, TX, USA, 2017, pp. 1-4.

doi: 10.1109/ICICDT.2017.7993526

Abstract: As device sizes are downscaled to nanometer, Random Telegraph Noise (RTN) becomes dominant. It is indespensable to accurately estimate the effect of RTN. We propose the RTN simulation method for analog circuits. It is based on the charge trapping model. We replicate the RTN-induced threshold voltage fluctuation to attach a variable DC voltage source to the gate of MOSFET by using Verilog-AMS. We confirm that drain current of MOSFETs temporally fluctuates. The fluctuations of RTN are different for each MOSFET. Our proposed method can be applied to estimate the temporal impact of RTN including multiple transistors. We can successfully replicate RTN-induced frequency fluctuations in 3-stage ring oscillators as similar as the measurement results [read more...]

Circuit Design and Simulation Project using eSim

Invitation to participate in Circuit Design and Simulation Project using eSim

The FOSSEE (Free and Open Source Software for Education) project based at lIT Bombay has initiated a Circuit Design and Simulation Project using esim (an open source EDA tool for circuit design, simulation, analysis and PCB design).

Interested candidates can take any solved electronic circuit from any source and redesign it using eSim and submit it to us. Candidates will be rewarded with certificates and honorarium after a review process. These circuits will also be published on our website under an appropriate open source license. 

For more details, please visit: http://esim.fossee.in/circuit-simulation-project