NIST Digital Library of Mathematical Functions

Project News

• 2016-12-21 DLMF Update; Version 1.0.14
• 2016-09-16 DLMF Update; Version 1.0.13
• 2016-09-09 DLMF Update; Version 1.0.12
• 2016-06-08 Future expansion
• More news

---

Foreword Preface Mathematical Introduction 1 Algebraic and Analytic Methods 2 Asymptotic Approximations 3 Numerical Methods 4 Elementary Functions 5 Gamma Function 6 Exponential, Logarithmic, Sine, and Cosine Integrals 7 Error Functions, Dawson’s and Fresnel Integrals 8 Incomplete Gamma and Related Functions 9 Airy and Related Functions 10 Bessel Functions 11 Struve and Related Functions 12 Parabolic Cylinder Functions 13 Confluent Hypergeometric Functions 14 Legendre and Related Functions 15 Hypergeometric Function 16 Generalized Hypergeometric Functions & Meijer G-Function 17 q-Hypergeometric and Related Functions 18 Orthogonal Polynomials 19 Elliptic Integrals

20 Theta Functions 21 Multidimensional Theta Functions 22 Jacobian Elliptic Functions 23 Weierstrass Elliptic and Modular Functions 24 Bernoulli and Euler Polynomials 25 Zeta and Related Functions 26 Combinatorial Analysis 27 Functions of Number Theory 28 Mathieu Functions and Hill’s Equation 29 Lamé Functions 30 Spheroidal Wave Functions 31 Heun Functions 32 Painlevé Transcendents 33 Coulomb Functions 34 3j, 6j, 9j Symbols 35 Functions of Matrix Argument 36 Integrals with Coalescing Saddles Bibliography Index Notations List of Figures List of Tables Software Errata

[paper] Pulsed I-V on TFETs: Modeling and Measurements

Pulsed I-V on TFETs: Modeling and Measurements
Quentin Smets, Anne Verhulst, Ji-Hong Kim, Jason P. Campbell, David Nminibapiel, Dmitry Veksler, Pragya Shrestha, Rahul Pandey, Eddy Simoen, David Gundlach, Curt Richter, Kin P. Cheung, Suman Datta, Anda Mocuta, Nadine Collaert, Aaron V.-Y. Thean, and Marc M. Heyns
in IEEE Transactions on Electron Devices, vol. 64, no. 4, pp. 1489-1497, April 2017
doi: 10.1109/TED.2017.2670660

Abstract: Most experimental reports of tunneling field-effect transistors show defect-related performance degradation. Charging of oxide traps causes Fermi-level pinning, and Shockley–Read–Hall (SRH)/trap-assisted tunneling (TAT) cause unwanted leakage current. In this paper, we study these degradation mechanisms using the pulsed I-V technique. Our simulations show pulsed I-V can fully suppress oxide trap charging, unlike SRH and TAT. We discuss several circuit-related pitfalls, and we demonstrate improved transfer characteristics by suppressing oxide trap charging using cryogenic pulsed I-V [read more...]

[mos-ak] [paper submission] Device and Circuit Compact Modeling TRACK4 at ESSDERC

Dear Compact Modeling Experts,

I would like to draw your attention to newly opened Device and Circuit Compact Modeling TRACK4 at ESSDERC. I was assigned to chair the track 4 with a group of the international reviewers. The new tract will cover a broad range of the compact modeling and its Verilog-A standardization topics (see below). I hope you will find these topic matching your current scientific work and R&D activities and you will eventually submit your conference paper for our new Device and Circuit Compact Modeling TRACK4 at ESSDERC.

Papers must not exceed four A4 pages with all illustrations and references included. All submissions must be received by 10 April, 2017. After selection of papers, the authors will be informed about the decision of the Technical Program Committee by e-mail by June 2, 2017. At the same time, the complete program will be published on the ESSDERC/ESSCIRC website.

I will be glad if you could also proactively promote our Device and Circuit Compact Modeling TRACK4 and also motivate and invite other compact modeling researchers and engineers to also submit their R&D scientific conference contributions. Please distribute my open invitation to all experts in your region.

Already now, I am looking forward to receive your conference submission and then meeting you at ESSDERC in Leuven.

-- thanks in advance -- wladek;
--
ESSDERC TRACK4: Device and Circuit Compact Modeling
TPC <http://www.esscirc-essderc2017.org/essderc-technical-program-committee>
Topics:<http://www.esscirc-essderc2017.org/essderc-call-for-papers>
Compact/SPICE modeling of electronic, optical, organic, and hybrid devices and their IC implementation and interconnection. Topics include compact/SPICE models and its Verilog-A standardization of the semiconductor devices (including Bio/Med sensors, MEMS, Microwave, RF, High voltage and Power), parameter extraction, compact models for emerging technologies and novel devices, performance evaluation, reliability, variability, and open source benchmarking/implementation methodologies. Modeling of interactions between process, device, and circuit design as well as Foundry/Fabless Interface Strategies.
---

WG160317

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at https://groups.google.com/group/mos-ak.
For more options, visit https://groups.google.com/d/optout.

Qucs Roadmap

The QUCS Roadmap should serve as base to track the status of each action point. Enhancements can be handled in two ways:

• For simpler enhancements an issue/bug ticket shall be created and referenced back here. The pertinent discussion and documentation should be done on the body of each ticket.
• For more complex enhancements a Qucs Enhancement Proposal should be created and reference back here.

The open action points can be further categorized concerning the difficulty or amount of work as (Easy, Medium, Hard) and priority (0-3, 0 is the highest). See the Port to Qt4 / Qt5 for an example. Tickets will be tracked individually and assigned to milestones leading to stable releases.

Stage 1 - Simple GUI and simulator  

Stage 2 - Implementation of powerful circuit analysis tools

Stage 3 - Support for more design and synthesis tools  

Stage 4 - Implementation of industry standard device models

Stage 5 - Design realization, production, verification

Read more about QUCS Roadmap

Bio-SPICE

Bio-SPICE: Biological Simulation Program for Intra- and Inter-Cellular Evaluation

 

Bio-SPICE, an open source framework and software toolset for Systems Biology, is intended to assist biological researchers in the modeling and simulation of spatio-temporal processes in living cells. In addition, our goal is to develop and serve a user community committed to using, extending, and exploiting these tools to further our knowledge of biological processes.

In collaboration with other Bio-SPICE, Community members, we will develop, license, distribute, and maintain a comprehensive software environment that integrates a suite of analytical, simulation, and visualization tools and services to aid biological researchers engaged in building computable descriptions of cellular functions. From disparate data analysis and information mining to experimental validation of computational models of cell systems, our environment will offer a comprehensive substrate for efficient research, collaboration, and publication.

Mission
Bio-SPICE, is intended for modeling and simulation of spatio-temporal processes in living cells. The goals of Bio-SPICE, are to support discovery through:

1. Developing computational and mathematical models of bio-molecular systems in cells capturing the nature of gene-protein interactions
2. Developing tools that can rapidly incorporate relevant experimental data and knowledge known in the literature to build models of pathways, networks, and spatial processes
3. Developing simulation tools for the dynamic analysis of bio-molecular systems
4. Creating an extensible framework for easy insertion of models and their refinement, as well as customization to specific mechanisms

In addition, our goal is to develop and serve a user community committed to using, extending, and exploiting these tools to further our knowledge of biological processes. In collaboration with other Bio-SPICE Community members, we will develop, license, distribute, and maintain a comprehensive software environment that integrates a suite of analytical, simulation, and visualization tools and services to aid biological researchers engaged in building computable descriptions of cellular functions. From disparate data analysis and information mining to experimental validation of computational models of cell systems, our environment will offer a comprehensive substrate for efficient research, collaboration, and publication [read more...]

[paper] III-V Channel Double Gate FETs

Compact Modeling of Charge, Capacitance, and Drain Current
in III-V Channel Double Gate FETs

C. Yadav; M. Agrawal; A. Agarwal; Y. S. Chauhan

in IEEE Transactions on Nanotechnology , vol.PP, no.99, pp.1-1
doi: 10.1109/TNANO.2017.2669092

Abstract: In this paper, we present a surface potential based compact modeling of terminal charge, terminal capacitance, and drain current for III-V channel double gate field effect transistor (DGFET) including the effect of conduction band nonparabolicity. The proposed model is developed accounting for the 2-D density of states and includes the effect of quantum capacitance associated with the low density of states channel material. In addition, model incorporates contribution of the first two subbands and efficiently captures the step like behavior appearing in the gate capacitance and trans-conductance with population of the higher sub-bands. The behavior of bias dependent terminal capacitances and drain current are verified with the numerical simulation data of InGaAs channel DGFET and shows a close agreement with the simulation data [read more...]

[mos-ak] [Final Program] Spring MOS-AK Workshop at DATE Conference in Lausanne, March 31, 2017

 Spring MOS-AK Workshop  

   at DATE Conference in Lausanne, March 31, 2017
     Final Program online http://mos-ak.org/lausanne_2017/   

 
 Together with the MOS-AK workshop chair, Dr. Jean-Michel Sallese, EPFL and International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the Spring MOS-AK Workshop which will be held during DATE Conference on March 31, 2017 in Lausanne (CH). The MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Important Dates:

• Preannouncement - Dec. 2016
  
• Call for Papers - Jan. 2017
  
• Final Workshop Program - Feb. 2017
  
• MOS-AK Workshop - March 31, 2017

Venue:

Swisstech Convention Centre Quartier Nord de l'EPFL Route Louis-Favre 2 CH-1024 Ecublens (CH)

Final Program of Spring MOS-AK/DATE workshop is available online
http://www.mos-ak.org/lausanne_2017/

Online MOS-AK/DATE Workshop Registration

https://www.date-conference.com/registration
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

WG280217

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at https://groups.google.com/group/mos-ak.
For more options, visit https://groups.google.com/d/optout.