Feb 28, 2017

[paper] Readout electronics for LGAD sensors

Readout electronics for LGAD sensors
O. Alonso,a N. Franch,a J. Canals,a F. Palacio,a M. López,a A. Vilà,a A. Diéguez,a
M. Carulla,b D. Flores,b S. Hidalgo,b A. Merlos,b G. Pellegrinib and D. Quirionb
aDepartment of Engineering: Section of Electronics, University of Barcelona,
C/ Martí i Franquès nº1, Barcelona, 08028 Spain
bInstituto de Microelectrónica de Barcelona — Centro Nacional de Microelectrónica (IMB-CNM),
Campus UAB, Cerdanyola del Vallès, Bellaterra, Barcelona, 08193 Spain
doi:10.1088/1748-0221/12/02/C02069

Abstract: In this paper, an ASIC fabricated in 180 nm CMOS technology from AMS with the very front-end electronics used to readout LGAD sensors is presented as well as its experimental results. The front-end has the typical architecture for Si-strip readout, i.e., preamplification stage with a Charge Sensitive Amplifier (CSA) followed by a CR-RC shaper. Both amplifiers are based on a folded cascode structure with a PMOS input transistor and the shaper only uses passive elements for the feedback stage. The CSA has programmable gain and a configurable input stage in order to adapt to the different input capacitance of the LGAD sensors (pixelated, short and long strips) and to the different input signal (depending on the gain of the LGAD). The fabricated prototype has an area of 0.865mm  0.965mm and includes the biasing circuit for the CSA and the shaper, 4 analog channels (CSA+shaper) and programmable charge injection circuits included for testing purposes. A first approach to find the proper dimensioning of the input transistor has been done using a Matlab script, where the transconductance value has been calculated with the EKV model

Acknowledgments This work has been partially funded by the Spanish national projects FPA2013-48387 and FPA2015-71292. In addition, this work has been done in the framework of RD50 CERN collaboration.

Feb 21, 2017

1-cent "lab on a chip" could save lives

Rahim Esfandyarpour, Stanford University, helped to develop a way to create a diagnostic "lab on a chip" for just a penny:
"I'm pretty sure it will open a window for researchers because it makes life much easier for them - just print it and use it," said Esfandyarpour. The results of this research were recently published in the journal Proceedings of the National Academy of Sciences [Source: Stanford Medicine]

[paper] Bipolar and MOS Transistors Under the Effect of Radiation

Measurements of the Electrical Characteristics of Bipolar and MOS Transistors
Under the Effect of Radiation
K. O. Petrosyants, L. M. SamburskiiI. A. KharitonovM. V. Kozhukhov
Meas Tech (2017) doi:10.1007/s11018-017-1100-z

ABSTRACT: The specific nature of the process of measuring the electrical characteristics of bipolar and metal-oxidesemiconductor (MOS) transistors subjected to the action of neutron, electron, and gamma irradiation is considered. An automated measurement system is developed. Examples illustrating the use of the system for investigations of the radiation hardness of transistors are presented and the parameters of SPICE models for use in circuit design (including SOI/SOS CMOS circuits with EKV-RAD macromodel) are determined.

Translated from Izmeritel’naya Tekhnika, No. 10, pp. 55–60, September, 2016 [read more...]

Feb 17, 2017

[call for papers] 2017 IEEE S3S Conference

S3S Conference 2017
Overview: This industry - wide event has gathered, for over 30 years, industry leaders and widely known experts, in a social - oriented environment. Our contributed papers and invited talks are focused on SOI Technology, Low - Voltage Devices/Circuits/Architectures, and 3D Integration. These 3 technologies will play a major role in tomorrow's industry as they enable application - tailored and Energy / Cost efficient circuit designs.
Important Dates
Paper Submission Deadline: May 22, 2017
Acceptance Notification: July 1, 2017

The conference at a glance
Monday to Wednesday, Oct. 16-18, 2017: Technical Sessions
Thursday, Oct.19: Fully - Depleted SOI Circuit Design; Full-day Tutorial
Tuesday, Oct.17: Monolithic 3D Half-day Tutorial

Scope: We welcome papers in the following areas:
Silicon On Insulator (SOI)
• Advanced Materials, Substrate and Processes
• Device Physics, Characterization and Modeling
• Device/Circuit Integration
• SOI Design, Circuits and Applications
• Non-Digital Devices and Applications (RF,
HV, Photonics, NEMS, MEMS, Analog...)
• New SOI Structures, Circuits and Applications
Low-Voltage Microelectronics
• Space-Based and Unattended Remote Sensors
• Biomedical Devices
• Low-Voltage Handheld/wireless systems
• Ultra-Low-Power Digital Computation
• Analog and RF Technologies
• Low Voltage Memory Technologies
• Energy Harvesting Techniques
• Asynchronous Circuits
• Novel Device and Fabrication Technology
3D Integration
• Low Thermal Budget Processing
• Fabrication Techniques and Bonding Methods
• Design and Test Methodologies
• Processes for Multi Wafer Stacking
• 3D IC EDA and Design Technology
• Heterogeneous Structures
• 3D Manufacturing and Logistics
• Reliability of 3D Circuits
• Fault Tolerant 3D Designs

Paper Submission:
Prospective authors should prepare a 2page abstract (follow online guidelines).
Acceptance is based on paper’s technical quality and relevance.

Conference manager contact Joyce Lloyd
6930 De Celis Pl., #36
Van Nuys, CA 91406
Tel: +1 818 795 3768
Fax: +1 818 855 8392

Feb 16, 2017

HiSIM-HV and HiSIM2 implemented into ngspice

ngspice (Open Source SPICE Circuit Simulator) supports latest versions of HiSIM_HV and HiSIM2 [read more...]
REF: 
[2] T. Ezaki, D. Navarro, Y. Takeda, N. Sadachika, G. Suzuki, M. Miura-Mattausch, H. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, and S. Miyamoto, “Non-quasi-static Analysis with HiSIM, a Complete Surface-potential-based MOSFET Model”, Proceedings of the 12 th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES’2005), 923-928 (2005.6), Invited Paper
[3] M. Miura-Mattausch, D. Navarro, Y. Takeda, H.J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi and S. Miyamoto, “MOSFET Modeling for RF Circuit Era”, Proceedings of the 11 th International Conference on Mixed Design Mixed Design of Integrat ed Circuits and Systems (MIXDES’2004), 62-66 (2004), Invited Paper
[5] Mattausch,  H.J.;  Umeda,  T.;  Kikuchihara,  H.;  Miura-Mattausch,  M.,  "The  HiSIM compact models of high-voltage/power semiconductor devices for circuit simulation," in Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on , vol., no., pp.1-4, 28-31 Oct. 2014
[6] Mattausch,  H.J.;  Miyake,  M.;  Ii zuka,  T.;  Kikuchihara,  H.;  Miura-Mattausch,  M.,  "The Second-Generation  of  HiSIM_HV  Compact  Models  for  High-Voltage  MOSFETs,"  in Electron Devices, IEEE Transactions on , vol.60, no.2, pp.653-661, Feb. 2013

Feb 10, 2017

[paper] Model for Organic Thin-Film Transistor

Physically Based Compact Mobility Model for Organic Thin-Film Transistor
T. K. Maiti, L. Chen, H. Zenitani, H. Miyamoto, M. Miura-Mattausch and H. J. Mattausch
in IEEE Transactions on Electron Devices, vol. 63, no. 5, pp. 2057-2065, May 2016.
doi: 10.1109/TED.2016.2540653

Abstract: A physically based compact mobility model for organic thin-film transistors (OTFTs) with an analysis of bias-dependent Fermi-energy (EF) movement in the bandgap (Eg) is presented. Mobility in the localized and extended energy states predicts the drain-current behavior in the weak and strong accumulation operations of OTFTs, respectively. A hopping mobility model as a function of the surface potential is developed to describe the carrier transport through localized energy states located inside Eg. The Poole-Frenkel parallel-field-effect mobility and vertical-field-effect mobility are considered to interpret the bandlike carrier transport in the extended energy states. The parallel field effect on mobility is more pronounced for shorter channel length OTFTs and is considered by developing a channel-length-dependent mobility model. The vertical field effect on mobility is included to account for the effect of mobility on carrier transport at high gate-voltage-induced fields. We also compared the model results with 2-D device simulations and measurements to verify the developed mobility model [read more...]

Workshop on biomedical applications at EPFL Lausanne

Data communication and remote powering for biomedical applications 
Workshop organized by Prof. Catherine Dehollain and Dr. Maria-Alexandra Paun
on February 24, 2017 at 09:00-17:00 in Room BC 01, EPFL Lausanne

Workshop Program
Time
Invited Speaker
Presentation Title
09:00-09:35
Professor Catherine DEHOLLAIN,
EPFL, Lausanne, RF IC group
“Remotely powered sensor networks for medical applications”
09:35-10:10
Dr. Maria-Alexandra PAUN, EPFL, Lausanne, RF IC group
“Modeling and analysis of antennas in cochlear implants”
10:10-10:45
Dr. Gürkan YILMAZ, EPFL, Lausanne, RF IC group
“Wireless Power Transfer and Data Communication for Intracranial Neural Implants. Case Study: Epilepsy Monitoring”
Coffee Break (30 minutes)
11:15-11:50
Dr. Mehrdad GHANAD,
EPFL, Lausanne, RF IC group
“Remotely-Powered Batteryless Implantable Local Temperature Monitoring System for Freely Moving Mice”
11:50-12:25
Francesca STRADOLINI,
EPFL, Lausanne, LSI laboratory
“On-line monitoring of aesthetics during surgery: opportunities and challenges”
12:25-13:00
Professor Adrian M. IONESCU, EPFL, Lausanne, Nanolab laboratory
“Wearable biosensors and their applications in future digital health”
LUNCH (90 minutes)
14:30-15:05
Dr. Wladek GRABINSKI,
MOS-AK Association (EU)
“FOSS TCAD/EDA simulation tools with molecular/bio/med modeling examples”
15:05-15:40
Dr. Albrecht LEPPLE-WIENHUES,
Valtronic Technologies SA
“Ear infection, drug injectors and blood donation: innovative medical device development”
15:40-16:15
Dr. Qing WANG,
CHUV, Lausanne
“Development of a flow-through telemetry implant for monitoring cardiovascular blood pressure in small rodents and human”
16:15-16:50
Professor Philippe RYVLIN, CHUV, Lausanne
“Wearable devices for neurological diseases: Towards more rigorous clinical evaluation”
Concluding remarks (10 minutes)