Dec 28, 2016

FOSS CAD research is in the spotlight

The conference paper "FOSS as an efficient tool for extraction of MOSFET compact model parameters" reached 20 reads at the researchgate.net

FOSS as an efficient tool for extraction of MOSFET compact model parameters
D. Tomaszewski, G. Głuszko, M. Brinson, V. Kuznetsov and W. Grabinski
MIXDES 2016, Lodz, pp. 68-73.


Abstract—A GNU Octave – based application for device-level compact model evaluation and parameter extraction has been developed. The applications main features are as follows: experimental I-V data importing, generating input data for different circuit simulation programs, running the simulation program to calculate I-V characteristics of the specified models, calculating model misfit and its sensitivity to selected parameter variation, and the comparison of experimental and simulated characteristics. Measured I-V data stored by different measurement systems are accepted. Circuit simulations may be done with Ngspice, Qucs and LTSpiceIV. Selected aspects of the application are presented and discussed. 

Dec 27, 2016

Ken Shirriff Takes Us Inside the IC, For Fun https://t.co/QScTdhgFXV #papers


from Twitter https://twitter.com/wladek60

December 27, 2016 at 09:24PM
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J-EDS Comes of Age https://t.co/4HNl9cQhzh #papers


from Twitter https://twitter.com/wladek60

December 27, 2016 at 01:07PM
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Dec 25, 2016

Special Issue of Solid-State Electronics, dedicated to EUROSOI-ULIS 2016 https://t.co/fFD9GehZEP #papers #feedly


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December 25, 2016 at 09:14PM
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Dec 20, 2016

[paper] Analysis and Compact Modeling of Negative Capacitance Transistor

Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current
and Negative Output Differential Resistance
Part II: Model Validation
Girish Pahwa, Student Member, IEEE, Tapas Dutta, Member, IEEE, Amit Agarwal,
Sourabh Khandelwal, Member, IEEE, Sayeef Salahuddin, SM IEEE,
Chenming Hu, IEEE Fellow, and Yogesh Singh Chauhan, SM IEEE 
in IEEE Transactions on Electron Devices, vol. 63, no. 12, pp. 4986-4992, Dec. 2016

doi: 10.1109/TED.2016.2614436

Abstract: In this paper, we show a validation of our compact model for negative capacitance FET (NCFET) presented in Part I. The model is thoroughly validated with the TCAD simulations with respect to ferroelectric thickness scaling and temperature effects. Interestingly, we find that an NCFET with PZT ferroelectric of a large thickness provides a negative output differential resistance in addition to an expected high ON current and a sub-60 mV/decade subthreshold swing. The model is also tested for the Gummel symmetry and its transient capabilities are highlighted through a ring oscillator circuit simulation.

[read more at IEEE Xplore]

Dec 19, 2016

[Call for Papers] ESSCIRC–ESSDERC 2017



September 11-14, 2017
LEUVEN - Belgium
www.esscirc-essderc2017.org

ESSCIRC–ESSDERC annual Conference is the most important European forum for the presentation and discussion of recent advances in solid-state devices and circuits: MAKE SURE TO BE PART OF IT!


LOCAL SCIENTIFIC SECRETARIAT
​Cor Claeys (imec, BE) | General Chair
Chantal Deboes (imec, BE) | ESSDERC Chair
Danielle Vermetten (KU Leuven, BE) | ESSCIRC Chair

ORGANIZERS   

TECHNICAL CO-SPONSORSHIP
ESSDERC FINANCIAL SPONSOR 
ESSCIRC FINANCIAL SPONSOR 
DIAMOND SPONSOR  

ORGANIZING SECRETARIAT: Sistema Congressi s.r.l. 










Dec 16, 2016

[online] Verilog-AMS Quick Reference and Tutorials

Verilog-AMS is a hardware description language that can model both analog and digital systems. The official description of the Verilog-AMS language is contained in the Verilog-AMS Language Reference Manual.

This site is designed to be your quick reference guide for Verilog-A and Verilog-AMS. The reference material is not complete at this point, but is still quite usable. Over time the reference material should fill out and be supplemented with useful application notes and annotated models that will help you learn to use Verilog-A/MS more effectively. The emphasis is very much on analog and mixed-signal modeling. If you are looking for information on synthesis or the obscure corners of the Verilog language, you must look elsewhere
Both Ken & Henry at Designer’s Guide Consulting aim to make www.VerilogAMS.com your everyday source for information on Verilog-A/MS. Please take a look around, and tell your friends and co-workers. If you have questions about Verilog-AMS, feel free to ask them on
the forum at designers-guide.org.