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Synopsys, Inc. (
SNPS),
a global leader providing software, IP and services used to accelerate
innovation in chips and electronic systems, today announced immediate
availability of its comprehensive solution for FinFET-based
semiconductor designs. The solution includes a range of DesignWare
®Embedded Memory and Logic Library IP; silicon-proven design tools from the Galaxy
™
Implementation Platform; and foundry-endorsed extraction, simulation
and modeling tools. It also includes TCAD and mask synthesis products
used by foundries for FinFET process development. The three-dimensional
structure of FinFET devices represents a significant change in
transistor manufacturing that impacts design implementation tools,
manufacturing tools and design IP. Developed over a period of five years
through engineering collaboration with leading foundries, research
institutes and early adopters, Synopsys' FinFET solution delivers
production-proven technologies to manage the change from planar to 3-D
transistors. The full-line solution provides a strong foundation of EDA
tools and IP needed to accelerate deployment of FinFET technology which
offers improved power, performance and area for semiconductor designs.
"Synopsys continues to make significant investments to develop a
complete solution for adoption of new process geometries and devices,
including FinFETs," said Antun Domic, senior vice president and general
manager of Synopsys' Implementation Group. "Synopsys' extensive
collaboration with all the partners within the FinFET ecosystem,
including foundries, early adopters and research institutions, allows us
to deliver best-in-class technologies and to enable the market to
realize the full potential of this new transistor design."
"With our new 14nm-XM offering, we have accelerated our leading-edge
roadmap to deliver a FinFET technology optimized for the expanding
mobile market," said Gregg Bartlett, senior vice president, chief
technology officer at GLOBALFOUNDRIES. "Collaboration with partners has
been a key element of our ability to deliver this innovative FinFET
solution. We have collaborated early with Synopsys in multiple areas,
including modeling of the FinFET devices in HSPICE. We continue our
collaboration to accelerate adoption of FinFET technology for our mutual
customers."
"Our FinFET collaboration with Synopsys is key to maintaining our
semiconductor leadership position," said Dr. Kyu-Myung Choi, senior vice
president of System LSI Infrastructure Design Center, Samsung
Electronics Co., Ltd. "Our foundry and semiconductor design expertise,
combined with Synopsys' broad EDA tool and IP development experience
enabled us to address FinFET-related challenges effectively. We continue
to engage in strong collaboration to maximize the benefits of FinFET
technology."
"Very early on, we successfully demonstrated the power and
performance benefits of using FinFET 3-D transistors," said Dr. Chenming
Hu, distinguished professor of microelectronics at University of
California, Berkeley, widely regarded as the pioneer of FinFET
technology. "To make these demonstrations possible, my team worked
closely with Synopsys R&D on a number of areas including device
simulation. We continue to collaborate with Synopsys to deliver more
innovations for FinFET deployment."
FinFET-ready IP Working closely with leading foundries
for more than five years enabled Synopsys to gain design expertise and a
deep understanding of IP architectures. This close collaboration has
resulted in the successful deployment of Synopsys' DesignWare Embedded
Memory and Logic Library IP solutions on FinFET to key customers. A
broader range of IP is planned for development in 2013. The DesignWare
Embedded Memory and Logic Library IP is architected to achieve the full
benefits of the FinFET technology, delivering superior results in the
areas of performance, leakage and dynamic power, and low voltage
operation.
FinFET-ready Design Tools The shift from planar to
FinFET-based 3-D transistors is a significant change that requires close
R&D collaboration among tool developers, foundries and early
adopters to deliver a strong EDA foundation. Developed through a
multi-year collaboration with FinFET ecosystem partners, Synopsys'
solution accelerates time to market of FinFET-based designs. The
comprehensive solution includes IC Compiler for physical design, IC
Validator for physical verification, StarRC
™ for parasitic extraction, SiliconSmart for characterization, CustomSim
™ and FineSim for FastSPICE simulation and HSPICE
® for device modeling and circuit simulation.
FinFET-ready Manufacturing Tools The small geometries
and 3-D nature of FinFETs require new approaches to optimize device
performance and leakage, and to address the effect of process
variations. Target device performance and leakage is achieved through
the optimization of the fin geometry, stress engineering and other
factors. Process variations stem from random dopant fluctuations, line
edge roughness, layout-induced stress and other sources, which together
impact device and circuit performance. Synopsys has been collaborating
with foundries on the Sentaurus
™ TCAD and Proteus
™
mask synthesis products to address these issues. The Sentaurus product
line enables foundries to optimize FinFET processing and design devices
that meet the performance and leakage targets while mitigating the
impact of process variation. The Proteus product line provides foundries
with a comprehensive solution for performing full-chip proximity
corrections.
