Jan 3, 2012

Price per transistor on a chip

The price per transistor on a chip has dropped dramatically since Intel was founded in 1968. Some people estimate that the price of a transistor is now about the same as that of one printed newspaper character.

Intel has shipped over 200 million CPUs using high-k/metal-gate transistors – the kind used in 32nm processors -- since the technology was first put into production in November 2007. This translates to over 50,000,000,000,000,000 (50 quadrillion) transistors, or the equivalent of over 7 million transistors for every man, woman and child on earth. [more]

25th ICMTS Conference

SAN DIEGO March 19-22, 2012
Note: This program is subject to change without notice. Final printed version of program will be available at the conference.

Scientific employee, PhD student, or postdoc at TU Dresden

in circuit design 
on organic, flexible, roll-to-roll-printed & plastic-based semiconductor technologies 

The period of employment is governed by the Fixed Term Research Contracts Act (Wissenschaftszeitvertragsgesetz - WissZeitVG). The position is in the frame of the FLEXIBILITY (Flexible Multifunctional Bendable Integrated Light-Weight Ultra-Thin Systems) project funded by the EU involving 7 industry partners and 4 research institutions. PhD students will find excellence prerequisites for an innovative PhD thesis. The first wireless communication receiver fully integrated in a piece of plastic foil (without the need for a silicon chip) will be developed. The project is coordinated by our chair and provides an excellent platform for interdisciplinary cooperation with industry partners. 
Tasks
Design (analyses, simulation, device modelling, layout, testing and documen-tation) of circuits and systems operating up to radio frequencies in novel OLAE (Organic and Large Area Electronics) and roll-to-toll printed technologies for wireless communications. The authoring of scientific publications and the participation at project meetings and international conferences are expected. The active involvement in project management is planned for postdocs. 
Requirements:
Excellent to good master, Dipl.-Ing. or PhD degree in microelectron-ics, electrical engineering, physics or chemistry. Knowledge in circuit design, inde-pendent and flexible working attitude, innovative and analytical thinking, strong commitment, communicative team-player, good English. Knowledge in the following areas is advantageous: Integrated circuit design, OLAE, device modelling, high frequency engineering, communications and semiconductor technologies, measure-ment techniques, German language.
Miscellaneous:
Applications from women are particularly welcome. The same applies to the disabled. Interested candidates are requested to submit concise application material including CV and copy of certificates per email in pdf format to Frank.Ellinger@tu-dresden.de [read more...]

Dec 22, 2011

Trends confirming IEDM (by Jerzy Ruzyllo)

Fresh from IEDM, my [JR] first thought is that it continues to be a great forum to interact with people speaking the same language (language of semiconductors, that is), to refresh all contacts, and to establish new ones. And that's why people who want to stay "in touch" are drawn to the meetings such as IEDM. With at least six sessions being ran in parallel even the most diligent attendee won't be able to listen to more than some 15% of all the talks given.  So, in terms of technical contents the best source of information is a Technical Digest containing all the papers presented (which, by the way, can be acquired at the fraction of the cost of attendence at the meeting). 
Still, it is not the same as the most valuable experience come from just being there. As far as technical content is concerned my [JR] first impression is that the IEDM 2011 was mostly confirming trends in semiconductor device science and engineering that are already established rather than bringing to the surface entirely new technical solutions. 
I [JR] will be more specific in this regard in the follow up blogs. [So, stay tuned...]

Dec 1, 2011

Synopsys to Acquire Magma Design Automation

I copy from Synopsys site:

MOUNTAIN VIEW, Calif., Nov. 30, 2011 /PRNewswire/ -- Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, has signed a definitive agreement to acquire Magma® Design Automation Inc. (Nasdaq:LAVA), a provider of chip design software headquartered in San Jose, California. Bringing together complementary technology, development and support capabilities will enable the combined company to more rapidly meet customer requirements linked to chip designs at both leading-edge and mature process nodes.

Under the terms of the merger agreement, Synopsys will acquire Magma for $7.35 per Magma share in cash, resulting in a transaction value of approximately $507 million net of cash and debt acquired. The boards of directors of both companies have unanimously approved the transaction.

The closing of the merger is subject to customary conditions, including approval by the stockholders of Magma as well as U.S. regulators. In the event the merger closes as expected in the second calendar quarter of 2012, Synopsys anticipates it to be modestly accretive to non-GAAP earnings per share in its fiscal 2012. Synopsys plans to fund the acquisition with a combination of cash and debt, with the specifics to be determined at the time of close.


"The dramatic rise in complexity of today's semiconductor designs for all process nodes requires an equally dramatic increase in designer productivity. Customers are either dealing with the very complex physics of 20-nanometer design or they are squeezing the last bit of performance and cost from designs at mature, high-value nodes. To achieve success, our customers are asking for more new EDA capabilities than ever before," said Aart de Geus, chairman and CEO at Synopsys. "This acquisition will enable Synopsys to accelerate the delivery of the technology our customers need to keep the overall cost of design in check."

Nov 20, 2011

[mos-ak] Final Program MOS-AK/GSA Washington DC Workshop on Dec.7 2011

Final Program MOS-AK/GSA Washington DC Workshop on Dec.7 2011
====================================================
http://www.mos-ak.org/washington_dc/

* Free On-line Registration Form:
http://www.mos-ak.org/washington_dc/registration.php

* Venue:
The George Washington University Marvin Center
800 21st Street, Northwest, Suite 302
Washington, DC 20052
http://gwired.gwu.edu/marvincenter

* Agenda:
http://www.mos-ak.org/washington_dc/
With panel discussion:
Compact Model Verilog-A Standardization Panel
Geoffrey J. Coram, ADI (Moderator)
Marek Mierzwinski, Tiburon Design Automation (Introduction)
Panelists
Walter R. Curtice, WRC Consulting
Carlos Galup-Montoro UFSC, Brazil
Keith Green, TI, Compact Modeling Council
Benjamin Iniguez, URV, FP7 COMON Network

Local Organizing MOS-AK/GSA Committee:
======================================
Mona Zaghloul, GWU
Can E. Korman, GWU
John Suehle, NIST

Extended MOS-AK/GSA Committee:
==============================
Wladek Grabinski, GMC Suisse; MOS-AK/GSA Group Manager
Chelsea Boone, Director of Research GSA
* MOS-AK/GSA North America:
Chair: Pekka Ojala, Exar Corporation
Geoffrey Coram, Analog Devices
Jamal Deen, U.McMaster
Roberto Tinti, Agilent EEsof Division
* MOS-AK/GSA South America:
Chair: Gilson I Wirth; UFRGS; Brazil
Prof. Carlos Galup-Montoro, UFSC; Brazil
Sergio Bampi, UFRGS, Brazil
Antonio Cerdeira Altuzarra, Cinvestav - IPN, Mexico
* MOS-AK/GSA Europe:
Chair: Ehrenfried Seebacher, austriamicrosystems AG
Alexander Petr, XFab
Benjamin Iniguez, URV
James Victory, Sentinel-IC
* MOS-AK/GSA Asia/Pacific:
Chair: Goichi Yokomizo, STARC, Japan
Sadayuki Yoshitomi, Toshiba, Japan
A.B. Bhattacharyya, JIIT, India
Xing Zhou, NTU, Singapore

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Nov 11, 2011

[mos-ak] BSIM EKV Workshop at EPFL Lausanne on Dec. 15-16, 2011

Invitation to

The Nano-Tera Workshop on the Next Generation MOSFET Compact Models
15-16 December, 2011, EPFL

The BSIM group recently proposed BSIM6 as the new MOSFET compact model
to eventually replace BSIM3, BSIM4 and PSP for next generation bulk
CMOS processes. Trying to take advantage of the charge based features
of EKV, the BSIM research team from University of California,
Berkeley, led by Prof. Chenming Hu and the EKV modeling team at EPFL,
led by Prof. Christian Enz, decided to jointly develop the new BSIM6
compact model.

The BSIM EKV partnership has been officially announced by Profs. Hu
and Enz at the last ESSDERC-ESSIRC Conference during the MOS-AK
Workshop <http://mos-ak.org/helsinki/#BSIM-EKV>. The Nano-Tera
Workshop on the Next Generation MOSFET Compact Models will convene all
the BSIM and EKV researchers as well as the experts from the industry
to give an update on the latest status of BSIM6 and EKV (and
eventually other models as well) to the modeling and designer
community.

The detailed workshop program is available at: <http://ekv.epfl.ch/
workshop>

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