Taipei International Convention Center (TICC)
Taipei, Taiwan
January 18, 2010
Advance Program available on-line
Jan 12, 2010
Job offer (PhD grant)
Title: Integrated circuit behaviour optimization based on predictive test
Conditions:
- Duration three years ( it could be extended to a fourth year)
- Salary 1300 € per month plus medical insurance
- Support for attending conferences
- Free registration in the Electronic Engineering Master courses, shared between the UIB and the UPC (see the web)
Requirements of the candidates:
- Graduate on Electronic Engineering, Physics or equivalent.
- Interested in developing a career in research
Contact: Prof. Eugenio Garcia Moreno (eugeni.garcia in the server uib.es)
The call is expected to occur in January 2010, but you can find information about the previous call (2009) about deadlines, conditions, requisites, etc. in this page.
Summary:
Advances in manufacturing technologies of CMOS integrated circuits have enabled obtaining the shrinkage of the device dimensions together with higher working frequencies at the expense of a greater dispersion in their characteristics. The impact of process variations specially affects the performance specifications of the analog and RF sections.
The main objective of this project is to develop design methods that allow to construct inherently robust circuits against manufacturing process variations. We intend to approach the problem from previous results already obtained by our group in predictive test. This test strategy consists in estimating the circuit performance parameters from indirect measurements, an approach easier to implement than by means of the standard methods.
The proposed solution consists, first, in implementing the elements to carry out the test process on the own chip; this is the well-known Built in Self Test technique. Then, the results of the predictive test are used to modify, either the value of a circuit element or the own structure of the circuit, with the aim of optimizing some of their performance specifications. Hence, self-adjustable or reconfigurable circuits are obtained.
Although the concept can be applied to any anlog circuit, its implementation has to be tailored for each kind of circuits. Initially it will be applied to two circuits: a low pass filter for a RF receiver (self-tuning) and a pipeline analog to digital converter (reconfiguration). Nevertheless, all through the project we will seek new objective circuits.
Conditions:
- Duration three years ( it could be extended to a fourth year)
- Salary 1300 € per month plus medical insurance
- Support for attending conferences
- Free registration in the Electronic Engineering Master courses, shared between the UIB and the UPC (see the web)
Requirements of the candidates:
- Graduate on Electronic Engineering, Physics or equivalent.
- Interested in developing a career in research
Contact: Prof. Eugenio Garcia Moreno (eugeni.garcia in the server uib.es)
The call is expected to occur in January 2010, but you can find information about the previous call (2009) about deadlines, conditions, requisites, etc. in this page.
Summary:
Advances in manufacturing technologies of CMOS integrated circuits have enabled obtaining the shrinkage of the device dimensions together with higher working frequencies at the expense of a greater dispersion in their characteristics. The impact of process variations specially affects the performance specifications of the analog and RF sections.
The main objective of this project is to develop design methods that allow to construct inherently robust circuits against manufacturing process variations. We intend to approach the problem from previous results already obtained by our group in predictive test. This test strategy consists in estimating the circuit performance parameters from indirect measurements, an approach easier to implement than by means of the standard methods.
The proposed solution consists, first, in implementing the elements to carry out the test process on the own chip; this is the well-known Built in Self Test technique. Then, the results of the predictive test are used to modify, either the value of a circuit element or the own structure of the circuit, with the aim of optimizing some of their performance specifications. Hence, self-adjustable or reconfigurable circuits are obtained.
Although the concept can be applied to any anlog circuit, its implementation has to be tailored for each kind of circuits. Initially it will be applied to two circuits: a low pass filter for a RF receiver (self-tuning) and a pipeline analog to digital converter (reconfiguration). Nevertheless, all through the project we will seek new objective circuits.
Jan 11, 2010
The Children of Cyberspace
"The Children of Cyberspace: Old Fogies by Their 20s" By Brad Stone:
My 2-year-old daughter surprised me recently with two words: “Daddy’s book.” She was holding my Kindle electronic reader [continue reading]
My 2-year-old daughter surprised me recently with two words: “Daddy’s book.” She was holding my Kindle electronic reader [continue reading]
Jan 9, 2010
Ph D student fellowship in semiconductor device modeling
There is an open call for international fellowships to pursue a Ph D in Spain (the so-called "Becas MAE-AECID" from the Spanish Ministry of Foreign Affairs and Cooperation).
We want to get one fellowship for a Ph D student position in the Department of Electronic Engineering in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in Tarragona , Spain. The subject of the Ph D would be o the development of new techniques of characterization and modeling of nanoscale semiconductor devices, in particular III-V transistors. It will be related to two European projects in which the hosting group participates.
The duration of the grant will be 4 years. The monthly salary will be 1000 Euro/month.
Candidates cannot be Spanish citizens nor residents in Spain. However, it is required that they
have at least a basic knowledge of the Spanish language.
The candidate should have a Bachelor or Master degree in Electrical Engineering, Electronic Engineering, Telecommunication Engineering or Physics. A good background in Semiconductor Physics, Semiconductor Devices, or Integrated Circuit Design will be highly appreciated.
Applicants must send to my e-mail address (benjamin.iniguez@gmail.com), and by January 17 2010, a CV together with
a copy of the academic certificates indicating the grades obtained for all subjects during their studies.
Tarragona is a medium city (100000 inhabitants) with a pleasant Mediterranean climate and many recreation opportunities (nice beaches, theme parks, nature preserves, mountain hiking, touristic resorts and facilities). It is located 100 km Southwest of Barcelona, and it is very well connected by train, bus, highways and even low cost flights from its own airport.
My research group in the Department of Electronic Engineering, Universitat Rovira i Virgili (URV) is one of the strongest groups in compact modeling in Europe. We are leading one European project on compact modeling of semiconductor devices (in which a total of 15 European universities and companies participate).
Additional information about the University and the department can be found at: http://www.urv.cat/ and sauron.etse.urv.es.
We want to get one fellowship for a Ph D student position in the Department of Electronic Engineering in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in Tarragona , Spain. The subject of the Ph D would be o the development of new techniques of characterization and modeling of nanoscale semiconductor devices, in particular III-V transistors. It will be related to two European projects in which the hosting group participates.
The duration of the grant will be 4 years. The monthly salary will be 1000 Euro/month.
Candidates cannot be Spanish citizens nor residents in Spain. However, it is required that they
have at least a basic knowledge of the Spanish language.
The candidate should have a Bachelor or Master degree in Electrical Engineering, Electronic Engineering, Telecommunication Engineering or Physics. A good background in Semiconductor Physics, Semiconductor Devices, or Integrated Circuit Design will be highly appreciated.
Applicants must send to my e-mail address (benjamin.iniguez@gmail.com), and by January 17 2010, a CV together with
a copy of the academic certificates indicating the grades obtained for all subjects during their studies.
Tarragona is a medium city (100000 inhabitants) with a pleasant Mediterranean climate and many recreation opportunities (nice beaches, theme parks, nature preserves, mountain hiking, touristic resorts and facilities). It is located 100 km Southwest of Barcelona, and it is very well connected by train, bus, highways and even low cost flights from its own airport.
My research group in the Department of Electronic Engineering, Universitat Rovira i Virgili (URV) is one of the strongest groups in compact modeling in Europe. We are leading one European project on compact modeling of semiconductor devices (in which a total of 15 European universities and companies participate).
Additional information about the University and the department can be found at: http://www.urv.cat/ and sauron.etse.urv.es.
Jan 8, 2010
Semiconductors: Today & Tomorrow
Semiconductors: Today & Tomorrow is a cycle of seminars, running from January to June 2010, that bring a closer insight about trends, challenges and opportunities in semiconductor technology. Presented by expert, industry professionals the seminars seek to inspire and motivate students and professors alike into new areas of research and development, and to foster an entrepreneurial spirit that looks at emerging opportunities in the industry.
Registration on-line
Registration on-line
Jan 7, 2010
[mos-ak] C4F MOS-AK/GSA Rome Workshop
C4F MOS-AK/GSA Workshop: http://www.mos-ak.org/rome/
The IEEE Electron Devices Society is sponsoring coming MOS-AK/GSA
Workshop to be held in cooperation with the Faculty of Engineering,
Sapienza Università di Roma. The MOS-AK/GSA Workshop is HiTech forum
to discuss the frontiers of the electron devices modeling with
emphasis on simulation-aware models. Original papers presenting new
developments and advances in the compact/spice modeling and its
Verilog-A standardization are solicited. Suggested topics include (but
are not limited to):
* Compact Modeling (CM) of the electron devices
* Verilog-A language for CM standardization
* New CM techniques and extraction software
* CM of passive, active, sensors and actuators
* Emerging Devices, CMOS and SOI-based memory cells
* Microwave, RF device modeling, high voltage device modeling
* Nanoscale CMOS devices and circuits
* Technology R&D, DFY, DFT and IC Designs
* Foundry/Fabless Interface Strategies
On-line abstract submission is open with the deadline on Feb. 15, 2010
http://www.mos-ak.org/rome/abstracts.php
Selected best MOS-AK papers will be published in a special issue of
the Microelectronics Journal:
http://www.elsevier.com/wps/find/journaldescription.cws_home/405904/description#description
Further details and updates: http://www.mos-ak.org/rome/
==========================================================
* Tarragona: June'10 www.compactmodelling.eu
* Wroclaw: June 24-26 www.mixdes.org/Special_sessions.htm
* Seville: Sept. 18 www.mos-ak.org
==========================================================
Jan 4, 2010
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