Papers on IEEE Trans on Electron Devices (Aug 2008)

Well, it seems that this has been a very productive issue:

Accurate Statistical Description of Random Dopant-Induced Threshold Voltage Variability
Millar, C. Reid, D. Roy, G. Roy, S. Asenov, A. (link)

Analytical Threshold Voltage Model for Double-Gate MOSFETs With Localized Charges
Kang, H. Han, J.-W. Choi, Y.-K. (link)

Origin of the Asymmetry in the Magnitude of the Statistical Variability of n- and p-Channel Poly-Si Gate Bulk MOSFETs
Asenov, A. Cathignol, A. Cheng, B. McKenna, K. P. Brown, A. R. Shluger, A. L. Chanemougame, D. Rochereau, K. Ghibaudo, G. (link)

A Charge-Based Model for Long-Channel Cylindrical Surrounding-Gate MOSFETs From Intrinsic Channel to Heavily Doped Body
Liu, F. He, J. Zhang, L. Zhang, J. Hu, J. Ma, C. Chan, M. (link)

Drain Current Model Including Velocity Saturation for Symmetric Double-Gate MOSFETs
Hariharan, V. Vasi, J. Rao, V. R. (link)

A Unified Analytic Drain–Current Model for Multiple-Gate MOSFETs
Yu, B. Song, J. Yuan, Y. Lu, W.-Y. Taur, Y. (link)

A Quasi Two-Dimensional Conduction Model for Polycrystalline Silicon Thin-Film Transistor Based on Discrete Grains
Wong, M. Chow, T. Wong, C. C. Zhang, D. (link)

Simulation of the Impact of Process Variation on the Optimized 10-nm FinFET
Khan, H. R. Mamaluy, D. Vasileska, D. (link)

Investigation of the Transport Properties of Silicon Nanowires Using Deterministic and Monte Carlo Approaches to the Solution of the Boltzmann Transport Equation
Lenzi, M. Palestri, P. Gnani, E. Reggiani, S. Gnudi, A. Esseni, D. Selmi, L. Baccarani, G. (link)

A Physical Model of High Temperature 4H-SiC MOSFETs
Potbhare, S. Goldsman, N. Lelis, A. McGarrity, J. M. McLean, F. B. Habersat, D. (link)

3C-Silicon Carbide Nanowire FET: An Experimental and Theoretical Approach
Rogdakis, K. Lee, S.-Y. Bescond, M. Lee, S.-K. Bano, E. Zekentes, K. (link)

Characterization, Modeling, and Application of 10-kV SiC MOSFET
Wang, J. Zhao, T. Li, J. Huang, A. Q. Callanan, R. Husna, F. Agarwal, A. (link)

Nice papers (July, 2008)

No, we're not dead, but overworked... Here you have some nice papers, from various sources, including one which is unexpected...

A simple analytical model for the front and back gate threshold voltages of a fully-depleted asymmetric SOI MOSFET
Chung Ha Suh, Solid-State Electronics (abstract)

Analysis and Modeling of Threshold Voltage Mismatch for CMOS at 65 nm and Beyond
Jeffrey B. Johnson, Terence B. Hook, and Yoo-Mi Lee, IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 7, JULY 20 (abstract)

An Analytical Model Based on Surface Potential for a-Si:H Thin-Film Transistors
Yuan Liu, Student Member, IEEE, Ruo-he Yao, Bin Li, Member, IEEE, and Wan-Ling Deng, JOURNAL OF DISPLAY TECHNOLOGY, VOL. 4, NO. 2, JUNE 2008 (abstract)

Papers on the IEEE TED, vol 55 (7)

Some nice papers:

An Analytical Gate Tunneling Current Model for MOSFETs Having Ultrathin Gate Oxides
Mondal, I.; Dutta, A. K.
Abstract

A Fully Three-Dimensional Atomistic Quantum Mechanical Study on Random Dopant-Induced Effects in 25-nm MOSFETs
Jiang, X.-W.; Deng, H.-X.; Luo, J.-W.; Li, S.-S.; Wang, L.-W.
Abstract

A Physical-Based PSPICE Compact Model for Poly(3-hexylthiophene) Organic Field-Effect Transistors
Meixner, R. M.; Gobel, H. H.; Qiu, H.; Ucurum, C.; Klix, W.; Stenzel, R.; Yildirim, F. A.; Bauhofer, W.; Krautschneider, W. H.
Abstract

IEEE International Workshop on Compact Thin-Film Transistor Modeling for Circuit Simulation

The first IEEE International Workshop on Compact Thin-Film Transistor Modeling for Circuit Simulation will be held in the Moller Center, in Cambridge, UK, on September 11-12 2008.

This interesting workshop is organized by the IEEE EDS Compact Modeling Technical Committee, in collaboration with the London Center for Nanotechnology, University College of London, UK, the Electrical Engineering Division, Engineering Department, Cambridge University, UK, and the IEEE UK-RI (AP/ED/LEO/MTT) joint Chapter.

Compact modeling of TFTs has become nowadays a very hot topic, due to the extension of the applications of TFTs. This workshop will provide a forum for discussions and current developments on compact TFT modeling.

Topics include:

• Physics of TFTs and operating principles
• Compact TFT device models for circuit simulation
• Model implementation and circuit analysis techniques
• Model parameter extraction techniques
• Applications of compact TFT models in emerging products
• Compact models for interconnects in active matrix flat panels

The deadline for abstract submission is July 15.

I will give an invited presentation in this workshop. And there will be other interesting invited presentations.

This is the first workshop that is devoted to compact TFT modeling. I recommend the TFT modeling and TFT circuit design communities to attebnd this workshop.

Besides, in conjunction with the workshop on “Compact TFT Modeling for Circuit Simulation,” IEEE Electron Devices Society (EDS) Compact Modeling Technical Committee (CMTC) in collaboration with IEEE UK-RI AP/ED/LEO/MTT Chapter has organized EDS mini-colloquia (MQ) on September 12, 2008 at Moller Centre, Cambridge, UK.

SINANO-NANOSIL Workshop

The SINANO-NANOSIL Workshop will take place in Edinburgh on September 19th, 2008, during the ESSDERC-ESSCIRC Conference.

This Workshop, continuation of the former SINANO Workshop, is a very valuable discussion forum in the area of nanoelectronics devices. The SINANO-NANOSIL Workshop is supported by the SINANO Institute, which is a new European entity created by the main laboratories of the European academic community working in nanoelectronics, and by the European Network of Excellence NANOSIL which targets Silicon-based Nanodevices and is funded by the European Commission for the 7th Framework Programme, from 2008 to 2011. The former SINANO Workshop was funded by the prebvious Network of Excellence, called SINANO.

The program of the SINANO-NANOSIL Workshop consists of several presentations given by a number of representatives of NANOSIL partners:

9:00 New channel materials for ultimate CMOS
Siegfried Mantl (Institut für Bio- und Nanosysteme, Forschungszentrum Juelich)

9:30 Innovative device architectures for Nanoscale CMOS
Nadine Collaert (IMEC)

10:00 Coffee break

10:30 Comparative analysis of Stress-induced performance enhancement in NMOS and PMOS transistors
David Esseni (Udine University)

11:00 Characterization methods for Nanodevices
Sorin Cristoloveanu (IMEP)

11:30 Emerging Nanotechnology for integration of Nanostructures in Nanoelectronic devices
Thierry Baron (LTM)

12:00 Lunch

13:30 Small Slope Switches
Adrian Ionescu (EPFL)

14:00 3D Multichannels and stacked Nanowires Technologies
Thomas Ernst (LETI)

14:30 Carbon Nanotube - Silicon heterojunctions for Nanoelectronics and Nanosensors
Jimmy Xu (Brown University)

15:00 Atomic functionalities in Silicon devices: go beyond the FET by using single dopants and artificial silicon atoms
Marc Sanquer (INAC)

15:30 End of the Workshop

AM-FPD'08

The 15th International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD-08, former AM-LCD) will be held from July 2 to 4 2008 at the National Museum of Emerging Science and Innovation (Miraikan), Tokyo, Japan.

AM-FPD has extended the goals of former AM-LCD workshop in order to address, apart from AM-LCD technology, AM-OLED displays and other AM-FPD technologies. The topics of AM-FPD also include TFT devices, circuits and systems, LC technologies, related materials and crystallization.

Besides, a symposium "Emerging Technologies for Future Displays" is scheduled. This symposium will consist of four sessions: "Basic properties for fututre TFTs", "Advanced TFT technologies for future applications", "Technologies for LCD" and "Future technologies for Organic Devices".

The authors of the best papers will be invited to submit extended versions of their papers for publication in the Japanese Journal of Applied Physics, in a special issue called "Active-Matrix Flatpanel Displays and Devices-TFT Technologies and FPD Materials".

AM-FPD is one of the top conferences in the field of TFTs. Papers are very interesting, and include several invited presentations.

A number of papers address TFT compact modeling. H. Ikeda (Sony, Japan) presents one paper entitled "Surface Potential-BAsed Polycrystalline- Silicon TFT Model for Circuit Simulation". M. Kimura (Ryukoku University, Japan) presents "Physical Model of Current-Voltage Characteristic for TFT".

Other papers address issues such as LCD & FPDs, TFT crystallization technologies, TFT process technologies, characterization and reliability of TFTs, OLEDs, Oxide Semiconductor TFTs, and new applications of TFTs

BMAS'08

The 2008 IEEE International Behavioral Modeling and Simulation Conference (BMAS 2008) will be held in San Jose, CA, on September 25-26, in conjunction with the 2008 Custom Integrated Circuits Conference (CICC), in the Doubletree Hotel in San Jose, at the heart of Silicon Valley.

BMAS addresses behavioral modeling and simulation for analog electronic circuits and systems. One of the main areas of topics is "Semiconductor Device Compact Modeling", which includes: " Compact device modeling lanuages and compilers", "Standard and new compact device models implemented in Verilog-A and VHDL-AMS", and "Compact device models for emerging technologies and topical issues (nano-devices, distributed thermal effect, leakaging issues, manufacturability, radiation effects, etc)".

The deadline for paper submission is June 30 2008.

For compact and behavioral modeling researchers, BMAS is no doubt a very interesting conference to attend, and for circuit designers, it is a very good complement to CCIC.