Sep 11, 2007

November 2007 issue of IEEE Transactions on Circuits and Systems, Part-I

This issue will be a special issue on circuits and computing architectures in the emerging area of Nanotechnology. Among other, I've found some papers that I think are worth a look:

Title: Modeling of the Electrical Conductivity of DNA
Authors: Vedrana Hodzic, Vildana Hodzic, Robert W. Newcomb

As they say in the abstract: "We have developed a PSpice model of the electrical behavior of DNA molecules for use in nanoelectronic circuit design. To describe the relationship between the current through DNA and the applied voltage we used published results of the direct measurements of electrical conduction through DNA molecules. The experimental dc current-voltage (I-V) curves show a nonlinear conduction mechanism as well as the existence of a temperature dependent semiconductive voltage gap. A weighted least-squares polynomial fit to the experimental data at one temperature, with fitted temperature dependent polynomial coefficient of the linear term, was used as a mathematical model of electrical behavior of DNA. An equivalent electrical circuit was created in PSpice in which DNA was modeled as a voltage-controlled current source described by the mathematical model that includes temperature dependence, GPOLY(T) . Using this model, PSpice simulations with this model generated current-voltage-curves at other temperatures that were in excellent agreement with experimental data"


Title: CNTFET Modeling and Reconfigurable Logic Circuit Design
Authors: Ian O'Connor, Junchen Liu, Frédéric Gaffiot, Fabien Prégaldiny, Christophe Lallement, Cristell Maneux, Johnny Goguet, Sebastien Frégonèse, Thomas Zimmer, Lorena Anghel, Trinh Dang, Régis Leveugle

This paper examines aspects of design technology required to explore advanced logic circuit design using CNTFET devices. An overview of current types of CNTFETs is given and highlights the salient characteristics of each. Compact modeling issues are addressed and new models are proposed implementing (i) a physics-based calculation of energy conduction sub-band minima to allow a realistic analysis of the impact of CNT helicity and radius on the dc characteristics and (ii) descriptions of ambipolar behavior in Schottky-Barrier CNTFETs and ambivalence in double-gate CNTFETs. Using the available models, the influence of the parameters on the device characteristics were simulated and analyzed. The exploitation of properties specific to CNTFETs to build functions inaccessible to MOSFETs is also described, particularly with respect to the use of double-gate CNTFETs in fine-grain reconfigurable logic.

Paper on Science

There is a paper on this month issue of Science from some people of IBM, stating that they have "seen" the dopant distribution in a nano-scale device. The point is, leaving apart the technique, that the dopant does not get an uniform distribution, even after annealing. See the paper: Imaging of Arsenic Cottrell Atmospheres Around Silicon Defects by Three-Dimensional Atom Probe Tomography, by Keith Thompson, Philip L. Flaitz, Paul Ronsheim, David J. Larson, and Thomas F. Kelly

Sep 10, 2007

IEEE Trans. on Electron Devices

This month's issue is a "Special Issue on Simulation and Modeling of Nanoelectronics Devices". That means that I will not look for papers, but I'll only say that all of them are quite interesting. There are papers on threshold voltage modeling, on modeling of statistical variations, on quantum effects,... So, have a look!

Papers on the Applied Physics Letters

I've found some interesting paper on this month's issue:

Estimation of electron traps in carbon-60 field-effect transistors by a thermally stimulated current technique, by Toshinori Matsushima, Masayuki Yahiro, and Chihaya Adachi

Ballistic quantum transport in a nanoscale metal-oxide-semiconductor field effect transistor, by Vijay K. Arora, Michael L. P. Tan, Ismail Saad, and Razali Ismail

Tuning of electrical characteristics in networked carbon nanotube field-effect transistors using thiolated molecules
, by Chun Wei Lee, Keke Zhang, H. Tantang, Anup Lohani, S. G. Mhaisalkar, Lain-Jong Li, T. Nagahiro, K. Tamada, Y. Chen

These are three quite different topics, but I think that they are interesting enough.

Sep 6, 2007

IEEE Awards

I've just received the list of the 2007 IEEE Awards, and I wanted to make a comment. First of all, many congratulations to dear Prof. Michael S. Shur, for his two (yes, TWO) awards. The first award is the Leon K. Kirchmayer Graduate Teaching Award, that goes to those able to show inspirational guidance of graduate students in all IEEE fields of interest. Prof. Shur obviously is a most than adequate recipient for this award. His second award (jointly with Arturas Zukauskas) is the Donald G. Fink Prize Paper Award, and goes to the authors of the most outstanding paper published by the IEEE.

I also want to congratulate Prof. Yannis P. Tsividis, who is the recipient of the 2007 Gustav Robert Kirchhoff Award, that goes to those providing outstanding contributions to the fundamentals of any aspect of electronic circuits and systems that has a long-term significance or impact. Again, Prof. Tsividis is a mythical figure in the field of Device Modeling.

In brief, many congratulations for them and for all the other recipients of the IEEE Awards!

Sep 5, 2007

Free Keithley Web Seminar on Measurement

This seminar covers precision test and measurement applications for an emerging class of low cost (<$1000 USD) 6½-digit digital multimeters. Learn how to assemble a testing error budget for various applications for electronic devices and products. Examples include simple test programming to support automatic acquisition and evaluation of measurement data, as well as basic front panel operation.

By participating in this seminar, you will learn and understand:

  • How to establish a measurement accuracy budget for an application
  • How to account for central and parasitic sources of error
  • How to match your accuracy requirements with the appropriate DMM
  • How to calculate system test uncertainties and errors

This seminar is recommended for development and test engineers and scientists who need to make high precision electrical measurements using widely available, highly accurate 6½-digit DMMs.

About the Presenter:

Chuck Cimino is the Marketing Director for Multi-Application Instruments at Keithley Instruments, Inc. in Cleveland, Ohio. He joined Keithley Instruments in 1981 and has held many positions, including Test Engineer, Design Engineer, Project Manager, and Product Marketer.
The seminar will be broadcasted over the internet and requires your registration prior to the event.

When is it?

Europe: Thursday, September 13, 2007
15:00 Central European Time
(UTC/GMT: 13:00)


To register for this FREE webcast seminar click here.

Sep 2, 2007

Primer Seminario en Nanoelectrónica y Diseño Avanzado 2007

A friend of mine (Francisco J. Garcia Sanchez) has sent me the announcement of the first Seminar on Nanoelectronics and Advanced Design to be held at the INAOE in Puebla, Mexico. Here you have the link: http://www-elec.inaoep.mx/castour2007

The program is VERY interesting, with five stellar speakers, and, best of all, the admision is free...

P R O G R A M

Dr. Francisco J. Garcia Sanchez, /Universidad Simón Bolivar, Caracas, Venezuela
De la Microelectrónica a la Nanoelectrónica: Una Visión de la Evolución de los Dispositivos Electrónicos.

Prof. Krishnendu Chakrabarty, /Duke University, USA
Modular Testing of Core-Based System-on-Chip Integrated Circuits.

Prof. Rajendra Singh, /Clemson University, South Carolina, USA
Nanotechnology and Pathways to Green Energy Conversion

Prof. Naveen K. Yanduru , /Design Manager, Texas Instruments, Inc. Dallas, Tx, USA
Front-ends in deep sub-micron CMOS with an example of a WCDMA, GSM/GPRS/EDGE receiver front-end without inter-stage SAW filter in 90nm CMOS.

Dr. Mauricio Terrones, /Advanced Materials Department, IPICyT, San Luis Potosí, México.
Recent Advances on N-doped Carbon Nanotubes: Applications and Biocompatibility

For more information:
Dr. J. Alejandro Díaz
ajdiaz@inaoep.mx
Tel y Fax: (222) 2470517