Showing posts with label workshop. Show all posts
Showing posts with label workshop. Show all posts

Nov 10, 2023

Cutting-Edge IC Design Workshop

U.S. - Japan Collaboration Workshop
(Phase-1)
Tuesday, December 5 2023; 8:00 - 12:00 AM  (JST)
Wednesday, December 6 2023; 8:00 - 12:00 AM (JST) 
Online

The semiconductor industry is facing a number of challenges in building a stable supply chain. The importance of semiconductors was reaffirmed at the global level, and various initiatives were announced to revitalize and support the semiconductor industry, including investment in infrastructure development and human resource development for cutting-edge foundries. Against this backdrop, it is hoped that the creation of next-generation semiconductor technology and the further expansion of the industry will be achieved based on strong cooperation between Japan and the United States. As a phase 1 toward this goal, this workshop will discuss cutting-edge IC design technologies such as open source IC design, ecosystem construction, and human resource development. This workshop was supported by the U.S. Consulate in Fukuoka.

Application deadline is December 12. Please apply individually for DAY-1 and DAY-1the following form (you can also apply for only one of them).
[Participation fee] Free
[Notice] Simultaneous interpretation is available in English and at ZOOM Webinar.

DAY-1: Dec. 5th, 8:00-11:35 AM (JST)
8:00 - 8:05 Opening Remark and Overview of the Workshop, Mehdi Saligane, University of Michigan, Koji Inoue, Kyushu University
8:05 - 8:10 Welcome Remarks from the U.S. Consulate in Fukuoka
8:10 - 8:40 TBD, Steve Kosier, Skywater
8:40 - 9:10 The Emerging Ecosystem of Open-Source IC Design: IEEE SSCS Activities and Future Goals, Boris Murmann, Chair of the SSCS TC OSE, University of Hawaii
9:10 - 9:40 Human resource development for Semiconductor Technologies in Fukuoka, Koji Inoue, Fukuoka Semiconductor Reskilling Center/Kyushu University, Hideharu Kanaya, Kyushu University,
9:40 - 9:50 Break
9:50 - 10:20 Lab to Fab in the Cloud: Semiconductor Innovation at Amazon, David Pellerin, AWS 
10:20 - 10:50 TBD, Kai Yick, Google Research ML
10:50 - 11:20 Analog and Mixed-Signal IC Design Automation, David Wentzloff, University of Michigan
11:20 - 11:30 Q&A + Panel Discussion
11:30 - 11:35 Conclusion, Mehdi Saligane, University of Michigan

DAY-2: Dec. 6th, 8:00-11:30 AM (JST)
8:00 - 8:05 Opening Remark and Overview of the Workshop, Mehdi Saligane, University of Michigan, Koji Inoue, Kyushu University
8:05 - 8:35 Innovation by Collaboration: CHIPS Alliance, Rob Mains, CHIPS Alliance, Linux Foundation 
8:35 - 9:05 Developing CMOS+X Platforms for Artificial Intelligence and Beyond, Brian Hoskins, NIST 
9:05 - 9:35 Agile-X: Agile Chip Design and Fabrication Platform, Makoto Ikeda, University of Tokyo
9:35 - 9:45 Break
9:45 - 10:15 The future of semiconductor : chips and chiplets, Dan J. Dechene, IBM Research
10:15 - 10:45 AI Chip Design Center – open hub for chip innovation -, Kunio Uchiyama, National Institute of Advanced Industrial Science and Technology  
10:45 - 11:15 Democratizing EDA Tooling and Chip Design, Johan Euphrosine, Google (Tentative)
11:15 - 11:25 Q&A + Panel Discussion
11:25 - 11:30 Conclusion and Overview of the phase-2 workshop activities, Mehdi Saligane, University of Michigan, Koji Inoue, Kyushu University

[お問い合わせ] ic-design-ws 'at' slrc.kyushu-u.ac.jp ( 'at' を @ で置き換えてください)

Nov 1, 2023

IWPSD 2023

XXII International Workshop on Physics of Semiconductor Devices
Research Park, IIT Madras, Chennai - 600036
Dec. 13-17, 2023


organised by
Indian Institute of Technology Madras
@ Research Park, IIT Madras

in association with
Society for Semiconductor Devices (SSD)
Semiconductor Society (India)

The XXII International Workshop on the Physics of Semiconductor Devices (IWPSD 2023) is being jointly organized by the Indian Institute of Technology Madras in collaboration with Society for Semiconductor Devices and Semiconductor Society (India). This series of biennial workshops, started in 1981, provides a global forum for interaction between scientists and technologists working in the area of semiconductor materials and devices.

The topics to be covered in the Workshop are, but not limited to:
  • 2D Materials and Devices
  • Crystal Growth and Epitaxy
  • Device Modelling and Simulation
  • Devices for Quantum Technology
  • II - VI and Oxide Semiconductors
  • III - V Semiconductors
  • Memory and Logic Devices
  • MEMS, NEMS and Sensors
  • Organic and Flexible Electronics
  • Photovoltaics
  • Power Semiconductor Devices
  • Optoelectronics
IWPSD 2023 Registration is open. Registration fees includes admission to all conference sessions, daily lunch and tea breaks, conference kit and dinner/banquet.

Contact: <admin.iwpsd2023@ee.iitm.ac.in>

Oct 9, 2023

[C4P] IJNM - 7th Sino MOS-AK Workshop

Call for Papers
Special issue on the 7th International Sino MOS-AK Workshop


Submission deadline: Sunday, 31 December 2023

The 7th International Sino MOS-AK Workshop was held on 11-13th August 2023 in Nanjing, China. MOS-AK working group has more than 20 years enabling  compact modeling  R&D exchange. For additional detailed info, please refer to MOS-AK website:
http://www.mos-ak.org/nanjing_2023/.

With the aggressive scaling of CMOS technologies and constantly emerging diversified devices, accurate device modeling technique poses severe challenge to circuit and system designers, in particular for RF/MW/mmW/THz/Power/optics. With this background, the workshop aims to strengthen a network and discussion forum among experts in the field, provide a forum for the presentation and discussion of the leading-edge research and development results of Analytical Modeling, Compact Modeling, Characterization and Simulation techniques for advanced devices, circuits and technologies. Modeling and validation technique of all solid-state devices, including, Si, III-V, power, nanoscale electronic structures and other related new devices are within the scope of the conference. The theme of MOS-AK is "Bridge of Process Technology and Integrated Circuits & Systems Design".

Topics for this call for papers include but not restricted to:

  • Advances in semiconductor technologies and processing (CMOS, SOI, FINFET, III-V, Wide band-gap)
  • CM of passive active, sensors, and actuators
  • Emerging Devices, photonic devices, CMOS, and SOI-based memory cell
  • RF/THz device and Power device modeling
  • Power device and Power integration
  • Reliability modeling
  • AI and machine learning in EDA & modeling application
  • Nanoscale CMOS devices and circuits
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • Open-source TCAD/EDA modeling and simulation
  • Technology R&D, DFY, DFT and IC Designs
  • Chiplet Modeling and Packaging-related modeling
  • Foundry/Fabless Interface Strategies, Open Access PDKs
  • DTCO & STCO-related EDA tools/technologies
  • Other related topics

Guest Editors:

  • Jun Zhang
    Nanjing University of Posts and Telecommunications (CN)
  • Yuehang Xu
    University of Electronic Science and Technology of China (CN)
  • Wladek Grabinski
    MOS-AK (EU)

Submission Guidelines/Instructions

Authors of papers presented at the conference will be invited to submit an extended paper by 31 December 2023 to a special issue of IJNM. Manuscripts for this special issue should adhere to the requirements for regular papers in IJNM as specified in the journal’s Author Guidelines. The manuscripts will be submitted via the IJNM manuscript submission site, https://wiley.atyponrex.com/journal/jnm. Authors must choose the special issue title from the dropdown list on the “Additional Information” tab.

SUBMIT NOW

Sep 25, 2023

[workshop] gdsfactory

gdsfactory workshop, UCSB Photonics Society
August 24, 2023 in Henley Hall, UCSB

The first gdsfactory hands-on workshop organized as part of the  UCSB  Photonics Society. Thomas Dorch from Freedom Photonics and Andrei Isichenko presented gdsfactory. Last year gdsfactory seminar by Joaquin Matres, the maintainer of gdsfactory - you can access the video recording here. This workshop was a hands on; things to do before the workshop

  1. Install anaconda python 3 on your computer. If you don't have it installed, the links below are for miniconda, a "lightweight" version of anaconda. Windows: link. Mac: link (select if Intel or M1).
  2. Download a Python IDE. Either Visual Studio Code or Pycharm. Personally I prefer VS Code
  3. Download klayout. Windows: link. Mac: link (works on M1 mac, Ventura 13.4).

gdsfactory team will be running the tutorial using python notebooks (.ipynb). These can be run through JupyterLab, VS code (install this extension), or through Google Colab. You have the option to skip all the steps above and run the notebooks entirely in Google Colab (but with some limitations in klayout integration). You can try it out using this notebooks in this repository, focused on workshop_part1.ipynb. In Google Drive you should have the option to select "open with Google Colaboratory"

Click the "Open in Colab" link above to get started, and save a copy of the notebook to your Google Drive.

Google Drive Links to the notebooks:

https://drive.google.com/file/d/1x6kHQ9nHb1HB4HOEiEr1BG_y5lQ8si3e/view?usp=sharing

https://drive.google.com/file/d/1Ppz-CDrFezfLTIAHeBLYopl6Q4oyt8a4/view?usp=sharing



Aug 14, 2023

[11k online viewers] 7th Sino MOS-AK/Nanjing

Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
7th Sino MOS-AK Workshop in Nanjing (CN)
August 11-13, 2023 (online/onsite)
Recent, consecutive, 7th Sino MOS-AK/Nanjing Workshop discussing the Compact/SPICE modeling and its Verilog-A Standardization reached 11k online viewers. The MOS-AK participants and online attendees have followed one day SiC-related device modeling training on August 11 featured presentations by experts currently working at Robert Bosch GmbH and then two days workshop with 24 R&D Compact/SPICE modeling presentations:




Mar 3, 2023

[C4P] SEMINATEC 2023

 

SEMINATEC 2023 Call for Papers

SEMINATEC 2023 will be held at the Institute of Physics Gleb Wataghin, IFGW, auditorium between March 29-31, 2023 as a continuation of previous workshops, all focused on technology trends in the areas of micro and nanotechnology. The goal of this event is to promote the interaction among industry, academy, research & development centers, government and students, all looking for real opportunities towards improving education, research, and technology.

Contributed papers will be selected based on submitted abstracts (up to two pages) in A4 format. Electronic submissions will only be accepted in pdf format and must be submitted prior to March 6, 2023 The notification of acceptance will be on March 12, 2023.

The XVII SEMINATEC welcomes the submission of original papers in all areas related to  

  • Optoelectronic devices
  • Optics and Photonic IC’s
  • Fabrication of micro & nano-structures
  • Microsystems
  • Devices modeling and characterization
  • Integrated circuits: design and testing
  • CAD and simulation

Abstract Submission  (To download the template, click  here Abstracts will be accepted in PDF format. Please fill the form below and upload your file. All fields required.

SEMINATEC is organized by the School of Electrical and Computer Engineering (FEEC), the Institute of Physics Gleb Wataghin (IFGW) and the Center for Semiconductors Components and Nanotechnologies (CCSNano) at the University of Campinas (UNICAMP), by the Integrated Systems Laboratory (LSI) at the University of São Paulo (USP) and by the Department of Electrical Engineering at FEI, with support/funding from the IEEE Electron Device Society (EDS) South Brazil Chapter, the EDS Student Chapter of UNICAMP and FEI and by the SSCS South Brazil Chapter. The event is also supported by INCT’s NAMITEC, SBMICRO, FAPESP’s Integrated Photonics Devices (iPhD) and Integrated Photonics Lab (LIF SISFOTON).

Jul 21, 2021

[Final Program] 18th MOS-AK ESSDERC/ESSCIRC Workshop Grenoble; Sept. 6, 2021

MOS-AK ESSDERC/ESSCIRC Workshop Grenoble
Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
18th MOS-AK ESSDERC/ESSCIRC Workshop
Grenoble, Sept. 6, 2021

Together with local Host and MOS-AK Organizers as well as all the Extended MOS-AK TPC Committee, we invite you to the consecutive 18th MOS-AK ESSDERC/ESSCIRC Workshop. Scheduled Virtual/Online MOS-AK event aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors.

The MOS-AK Workshop Program is available online: 

Venue: Online MOS-AK Webinar;
use the online form/link below to register.

Online Registration is open
any related enquiries can be sent to registration@mos-ak.org

Post-workshop publications, selected, the best papers will be recommended for further publication in the special compact/SPICE modeling issue of the Solid State Electronics.

-- W.Grabinski; MOS-AK (EU)

Enabling Compact Modeling R&D Exchange

WG210721

Apr 7, 2021

[paper] Compact Modeling as a Bridge between Technologies and ICs


Compact Modeling as a Bridge 
between Scaled Semiconductor Technologies and Advanced Designs of the Integrated Circuits
AB Bhattacharyya and Wladek Grabinski
IETE Journal of Research 58(3):179-180 (May 2012)
DOI: 10.4103/0377-2063.97322

Abstract: The quality of the integrated circuits analysis, required in present contemporary design flows, is directly linked to the accuracy of its basic components—the Compact Model/Simulation Program with Integrated Circuit Emphasis (SPICE) Model. The compact/SPICE modeling is an essential research activity bridging scaled semiconductor technologies and advanced designs of the integrated circuits. To enable complete access to the new advanced semiconductor technologies, the designers have to frequently update their Computer-Aided Design (CAD) tools with accurate definition of the semiconductor device models that can be implemented into the CAD circuit simulators. The models must preferably be physics-based to account for complex dependencies of the device properties and defined in standard, high-level language, i.e., Verilog-A, to simplify access and implementation into the CAD tools. For the state of the art advanced CMOS technologies (analog, HV, SOI), both modeling and characterization are challenging tasks that will be emphasized in this special issue of Compact Modeling. (REF) Compact Modeling as a Bridge between Scaled Semiconductor Technologies and Advanced Designs of the Integrated Circuits. 

Available from: <http://www.mos-ak.org/india/>
and https://www.researchgate.net/publication/278384752_Compact_Modeling_as_a_Bridge_between_Scaled_Semiconductor_Technologies_and_Advanced_Designs_of_the_Integrated_Circuits

Mar 23, 2021

[mos-ak] [2nd Announcement and C4P] 3rd MOS-AK LAEDC Workshop (virtual/online) April 18, 2021

2nd Announcement and C4P

Together with  local organization team, International MOS-AK Board of R&D Advisers as well as all the Extended MOS-AK TPC Committee, we have the pleasure to invite to 3rd consecutive MOS-AK Compact/SPICE Modeling Workshop which will be organized as the virtual/online event on April 18, 2021 preceding the LAEDC Conference.

Planned virtual 3rd MOS-AK LAEDC Workshop aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors.

Venue: Virtual/Online at LAEDC Conference

Online Workshop Registration to be in April 2021, 
any related enquiries can be sent to registration@mos-ak.org

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:
  • Compact Modeling (CM) of the electron devices
  • Advances in semiconductor technologies and processing
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • Open Source (FOSS) TCAD/EDA modeling and simulation
  • CM of passive, active, sensors and actuators
  • Emerging Devices, Organic TFT, CMOS and SOI-based memory cells
  • Microwave, RF device modeling, high voltage device modeling
  • Nanoscale CMOS, BiCMOS, SiGe, GaN, InP devices and circuits
  • Technology R&D, DFY, DFT and reliability/aging IC designs
  • Foundry/Fabless Interface Strategies
Online Abstract Submission to be open, 
any related enquiries can be sent to abstracts@mos-ak.org

Important Dates: 
  • Call for Papers - Dec. 2020
  • 2nd Announcement - March 2020
  • Final Workshop Program - April 2020
  • MOS-AK Workshop April 18, 2021

WG23032021

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Mar 17, 2021

[Workshop] Democratizing IC Design, April 7th, 2021

Solid-State Circuits Directions Workshop:
Democratizing IC Design
Wednesday, April 7th, 2021 at 7:00 AM PT / 10:00 AM ET
This event is free and open to all

EVENT DESCRIPTION
Solid-State Circuits Directions (SSCD) is a new technical committee within the IEEE Solid-State Circuits Society (related article). Its charter is to promote forward-looking topics, build new communities and stimulate interaction with others. Following SSCD’s inaugural event on hardware security, the upcoming workshop will look at the new movement toward an open-source ecosystem for integrated circuit design.

Over the past several decades, society has strongly benefited from free and open-source software. More recently, the open-source spirit has expanded to hardware and has energized a new maker community that tinkers with embedded systems at the printed circuit board level. Groundbreaking developments have now also opened the door toward democratizing integrated circuit design.

Last year, Google, SkyWater and efabless have partnered to launch a shuttle program based on SkyWater’s SKY130 open-source process (130 nm CMOS). This technology is offered to the open community along with a complete design flow to enable designers to implement their ideas. This workshop will provide an overview of this program and highlight upcoming opportunities to benefit from it. Finally, it will showcase specific design work delivered by the community members and articulate a call to action for volunteers to design, teach and mentor.

AGENDA
7:00 AM PT- Welcome & Introductions (Boris Murmann, Stanford University)
7:05 AM PT- Fully open source manufacturable PDK for a 130nm process (Tim Ansell, Google)
7:35 AM PT- 45 Chips in 30 Days: Open Source ASIC at its best! (Mohamed Kassem, efabless)
7:55 AM PT- Design 1: Open Source eFPGA implementation in SKY130 (Xifan Tang, University of Utah)
8:25 AM PT- Design 2: Amateur Radio Satellite Transceiver (Thomas Parry, SystematIC Design)
8:55 AM PT- Call to Action: Need volunteers to design, teach and mentor
9:00 AM PT- Adjourn

Mar 10, 2021

[Workshop] Brain Inspired Computing; March 24, 2021

Workshop "Brain Inspired Computing”
March 24, 2021
Under the aegis of UKIERI and SPARC Scheme
Jointly Organized by
Dept. of EEE, The University of Sheffield (UK) 
Dept. of ECE, Indian Institute of Technology, Roorkee (IN)
and H2020 Project INFET

Why Brain Inspired Computing? Modern computers are based on the von Neumann architecture in which computation and storage are physically separated. It has been evaluated that, for many computing tasks, most of the energy and time are consumed in data movement, rather than computation. One promising solution is the brain-inspired architecture that leverages the distributed computing of neurons with localized storage in synapses. 
Registration Link Google Form

Coordinators:
Dr. Merlyne De Souza; PI, UKIERI, EEE Dept, University of Sheffield (UK)
Dr. Sanjeev Manhas; PI, SPARC, ECE Dept, IIT Roorkee (IN)

Schedule Details (UK times)
• 11:00-11:05am “Welcome note by organisers”, Merlyne De Souza, University of Sheffield (UK)
• 11:05-11:30am“Algorithm-circuits-device co-design for neuromorphic edge intelligence”, Melika Payvvand, ETH Zurich (CH)
• 11:30am-12pm “Adapting communication delays between neurons: A new type of brain plasticity”, Renaud Jolivet, University of Geneva (CH)
• 12-12.30pm “Self-adaptive and defect tolerant in-memory analogue computing with memristors”, Can Li, Hong Kong University (HK)
• 12:30-1:00 pm “In situ learning using intrinsic memristor variability”, Damien Querlioz, Université Paris-Saclay, France (F)
• 1:00-1:30pm “In memory hyper dimensional computing”, Abbas Rahimi, IBM Zurich (CH)
• 1:30pm-2:00pm “Introduction to NeuroSim: A Benchmark Tool for Compute-in-Memory
 Accelerator”, Shimeng Yu, Georgia Tech (USA)





Feb 4, 2021

FOSSEE 3-Day workshop on eSim

eSim (previously known as Oscad / FreeEDA) is a free/libre and open source EDA tool for circuit design, simulation, analysis and PCB design. It is an integrated tool built using free/libre and open source software such as KiCad, Ngspice and GHDL. eSim is released under GPL.

These workshops are being conducted by the expert faculty members of Indian Institute of Technology, Bombay. For registration and more details, visit our webpage. Participation certificate will be awarded to all the people who attend this workshop.

TimeSession
11 Feb 2021 (Installation and Simulation):
10:00 AM - 10:30 AMIntroductory Talk
by Prof. Kannan Moudgalya

10:30 AM - 10:45 AMExplaining the Workshop Procedure
10:45 AM - 11:05 AMBasics of circuit simulation by Prof. Mahesh Patil, IIT Bombay
11:05 AM - 12:00 NoonInstallation and system check for the installed software
12:00 Noon - 1:00 PMSpoken Tutorial session: Schematic Creation and Simulation
Lunch Break
2:00 PM - 3:00 PMSpoken Tutorial session: Simulating an Astable Multivibrator
3:00 PM - 4:00 PMPractice problem on Circuit Simulation
4:00 PM - 4:15 PMOverview of eSim - FOSSEE Team
4:15 PM - 4:45 PMDemo on PSpice to KiCad Converter - Sumanto, FOSSEE Fellow 2020 and FOSSEE Team
4:45 PM - 5:00 PMeSim on cloud - FOSSEE Team
5:00 PM - 5:30 PMFOSSEE activities under eSim
OvernightComplete the practice problems
12 Feb 2021 (PCB design and device modelling in eSim):
9:30 AM - 10:00 AMDiscussion of practice problems (Optional)
10:00 AM - 10:40 AMSpoken Tutorial session: Mapping Components with Footprints
10:40 AM - 11:20 AMSpoken Tutorial session: Setting Parameters for PCB designing
11:20 AM - 11:50 NooneSim software development: how it will benefit students, faculty and professionals? - FOSSEE Team
11:50 AM - 12:40 PMSpoken Tutorial session: Laying Tracks on PCB
12:40 PM to 1:00 PMSpoken Tutorial session: PCB Layout for Astable Multivibrator
Lunch Break
2:00 PM- 3:00 PMPractice problem: PCB design for a small circuit - 1 hour
3:00 PM - 4:00 PMLive session on Device modelling - FOSSEE Team
4:00 PM - 4:15 PMInvited talk: Prof. Sebin, Sreepathy Institute of Technology
4:15 PM - 4:30 PMInvited talk: Prof. Maheshwari, VIT Chennai
4:30 PM - 5:00 PMInvited talk: Wladek Grabinski, MOS-AK: FOSSS TCAD/EDA Tools
OvernightComplete the practice problems
13 Feb 2021 (Subcircuit builder and Introduction to NGHDL)
9:30 AM - 10:00 AMDiscussion of practice problems (Optional)
10:00 AM - 10:50 AMSpoken Tutorial session: Subcircuit Builder
10:50 AM - 11:40 AMSpoken Tutorial session: Editing a Subcircuit
11:40 AM - 12:30 PMSpoken Tutorial session: Uploading a spice Subcircuit file
12:30 PM - 1:00 PMMixed-signal simulation talk and demo: FOSSEE team
Lunch Break
2:00 PM - 3:00 PMPractice problem on Mixed-Signal circuit simulation using NGHDL
3:00 PM - 3:20PMHow NGHDL is extended for microcontrollers: Ashutosh Jha, FOSSEE Intern 2020
3:20 PM - 3:40 PMExpert Talk: Prof Madhav Desai, IIT Bombay
3:40 PM - 4:00 PMQ&A
4:00 PM - 4:15 PMExpert talk: Prof Kimberly Moraes
4:15 PM - 4:30 PMBenefits of contribution to FOSSEE's eSim efforts
4:30 PM - 5:00 PMFeedback and valedictory