FOSS Verilog-A Models Repository

Dietmar Warning, ngspice team, has announced his new github project VA-Models repository 
<https://github.com/dwarning/VA-Models>

These Verilog-A model code repository is a compilation of the most important models in the state of public FOSS availability. The intention is to have one place for model access and a platform for discussion and integration into simulators.

At the moment, the models will be compiled by script with openVAF and checked with ngspice version 39. Code changes are introduced only for convergence support or to fulfill Verilog-A language standard requirements. Model equations are untouched. But I am open to integrate code modifications for other compiler/simulator companions as far they are inline with actual LRM 2.4. Simple test case are provided, mainly to show general functionality of the compiled models. 

Don't hesitate to contact Dietmar Warning, ngspice team, if there is something wrong, especially in kind of legal aspects. All the contributions are welcome.

Call for Papers [dvconeurope] DVCon-Europe 2015

 DVCON EUROPE 2015

The Design and Verification Conference & Exhibition Europe (DVCon Europe) is the premier conference for system architects, concept engineers, software developers, design and verification engineers, and IP integrators to share the latest methodologies and technologies on the practical use of EDA and IP languages and standards used in electronic design.

The focus of this highly technical conference is on the industrial application of specialized design and verification languages such as SystemC, SystemVerilog, VHDL, UVM or e; assertions in SVA or PSL; the use of AMS languages; design automation using IP-XACT; and the use of general purpose languages C and C++.

CALL FOR PAPERS

This call for papers solicits presentations that are highly technical and reflect real life experiences in using EDA languages, standards, methodologies and tools. Industry applications of interest include (but are not limited to) automotive, mobile communication, aerospace, healthcare, chip-cards, consumer and power electronics. Submissions are encouraged in (but not restricted to) the four topic areas listed below. Low power techniques and design for functional safety (e.g., ISO 26262, DO-254) are pervasive and can be addressed in any of these topics areas.

Please submit your draft version of the paper by May 1, 2015. Detailed instructions on the paper requirements and submission process can be found on www.dvcon-europe.org. 

i-MOS version 201404 release

The i-MOS Team has announced  new release of the interactive Modeling and On-line Simulation
Platform (i-MOS), version 201404. In this release, there are several new services listed as follows:

• Integrating the model benchmark testing suites in Model page
• Including first three benchmark tests for model evaluations
• Constructing the Developer page for device model submissions
• Implementing one industry standard MOSFET model HiSIM2
• Uploading presentation files from IWCM 2014 for your references

For more details, please visit the i-MOS website.

Process for the Selection of the Next Generation Multigate Compact Models

The Compact Modeling Council (CMC) will start the process for the selection of a Multi-Gate MOSFET Compact Model with four-part standardization plan:

• Model pre-evaluation (reference data, test circuits, etc)
• Physical model accuracy evaluation
• Model functionality in IC simulation
• Formal CMC balloting

As the next steps the CMC Subcommittee finalizes process and model requirements documents, then generates data requirements document for solicit candidate models. Expect standardization effort to end by ~YE 2010.