Showing posts with label modeling challenges. Show all posts
Showing posts with label modeling challenges. Show all posts

Apr 17, 2014

Devices That You Definitely Will (and Just Might) Use: Emerging Transistor Technologies for the Near-and Long-Term

 WEDNESDAY June 04, 4:00pm - 6:00pm | Room 302 
 TRACK: EDA
 TOPIC AREA: EMERGING TECHNOLOGIES

 SPECIAL DAC SESSION 63: Devices That You Definitely Will (and Just Might) Use: Emerging Transistor Technologies for the Near-and Long-Term

Chair:  Michael Niemier; Univ. of Notre Dame, IN
Organizers:  Michael Niemier; Univ. of Notre Dame, IN
Xiaobo Sharon Hu; Univ. of Notre Dame, IN

Want to learn about the latest developments in FinFET-based processor design? What other transistor technologies might follow FinFETs and would they bring new design and modeling challenges? Come to this session to hear about both near- and long-term transistor technologies and their prospects for continuing Moore’s Law-based performance scaling trends. The session will begin with a discussion of FinFET technology; subsequent presentations will discuss tunnel transistors (TFETs) as well as other emerging FET technologies that could reenable voltage scaling. The session will conclude with a discussion of modeling efforts that consider the impact of new device technologies on von Neumann architectures as well as hybrid analog/digital circuits and architectures.

63.1 FinFET's and Their Implications for Design Now and in the Future

  • Speaker: Rob Aitken; ARM Ltd., San Jose, CA
    Greg Yeric; ARM Ltd., Austin, TX
    Brian Cline; ARM Ltd., Austin, TX
    Lucian Shifren; ARM Ltd., San Jose, CA

63.2 Emerging Devices for Logic: Can a Low-Power Switch Be Fast?

  • Speaker: Thomas Theis; IBM T.J. Watson Research Center, Yorktown Heights, NY

63.3 Energy Efficient Tunnel-FET Transistors for Beyond CMOS Logic

  • Speaker: Uygar Avci; Intel Corp., Portland, OR
    Daniel Morris; Intel Corp., Portland, OR
    Ian Young; Intel Corp., Hillsboro, OR

63.4 Steep Slope Devices: Enabling New Architectural Paradigms

  • Speaker: Vijaykrishnan Narayanan; Pennsylvania State Univ., State College, PA
    Karthik Swaminathan; Pennsylvania State Univ., State College, PA
    Huichu Liu; Pennsylvania State Univ., State College, PA
    Moon Seok Kim; Pennsylvania State Univ., State College, PA
    Xueqing Li; Pennsylvania State Univ., State College, PA
    Jack Sampson; Pennsylvania State Univ., University Park, PA

Apr 15, 2014

[mos-ak] [on-line publications] Spring MOS-AK Workshop in London

  
Recent, Spring MOS-AK Workshop at the London Metropolitan University was organized to discuss SPICE/compact modeling and its standardization with following Qucs GPL circuit simulation tutorial. The workshop's presentations are available on-line at <http://www.mos-ak.org/london_2014/>.
   
Please also distribute further information about next MOS-AK related events among all who are interested in the SPICE/compact modeling and its Verilog-A standardization:
Already now, I am looking forward to meet you at one of our MOS-AK modeling events, soon.

-- with regards - wladek for the Extended MOS-AK/GSA Committee;
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Arbeitskreis Modellierung von Systemen und Parameterextraktion 
Modeling of Systems and Parameter Extraction Working Group
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Over two decades of Enabling Compact Modeling R&D Exchange
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