Showing posts with label Verilog. Show all posts
Showing posts with label Verilog. Show all posts

May 26, 2023

[paper] Chip-Chat

Jason Blocklove, Siddharth Garg, Ramesh Karri, and Hammond Pearce^
Chip-Chat: Challenges and Opportunities in Conversational Hardware Design
arXiv preprint arXiv:2305.13243 [cs.LG] 22 May 2023

New York University, NY USA
^University of New South Wales Sydney, Australia

Abstract: Modern hardware design starts with specifications provided in natural language. These are then translated by hardware engineers into appropriate Hardware Description Languages (HDLs) such as Verilog before synthesizing circuit elements. Automating this translation could reduce sources of human error from the engineering process. But, it is only recently that artificial intelligence (AI) has demonstrated capabilities for machine-based end-to-end design translations. Commercially available instruction-tuned Large Language Models (LLMs) such as OpenAI’s ChatGPT and Google’s Bard claim to be able to produce code in a variety of programming languages; but studies examining them for hardware are still lacking. In this work, we thus explore the challenges faced and opportunities presented when leveraging these recent advances in LLMs for hardware design. Using a suite of 8 representative benchmarks, we examined the capabilities and limitations of the state of the art conversational LLMs when producing Verilog for functional and verification purposes. Given that the LLMs performed best when used interactively, we then performed a longer, fully conversational case study where a hardware engineer co-designed a novel 8-bit accumulator-based microprocessor architecture. We sent the benchmarks and processor to tapeout in a Skywater 130nm shuttle, meaning that these ‘Chip-Chats’ resulted in what we believe to be the world’s first wholly-AI-written HDL for tapeout.
Fig: Processor synthesis information - Above (a) Components. Left: (b) Final processorGDS render by ‘kLayout’, I/O ports on left side, grid lines = 0.001 um.

Opportunities: Still, when the human feedback is provided to the more capable ChatGPT-4 model, or it is used to co-design, the language model seems to be a ‘force multiplier’, allowing for rapid design space exploration and iteration. In general, ChatGPT-4 could produce functionally correct code, which could free up designer time when implementing common modules. Potential future work could involve a larger user study to investigate this potential, as well as the development of conversational LLMs specific to hardware design to improve upon the results.

Nov 14, 2017

7th All-Russian Workshop on CAD of IC Design

7th All-Russian Workshop on computer aided design (CAD) of integrated circuits (IC) to be held at NRNU MEPhI on December 12-14, 2017. The free workshop is organized by NRNU MEPhI jointly with Cadence Design Systems. The program and further information about the Workshop is available via site cad.mephi.ru.

Program 
(with timetable and detailed information in pdf format)
12 December 2017
08:45 - 09:15Registration (University entrance)
09:30 - 13:00Conference hall 3rd floor of the main lecture building
- Synthesis in Genus (28nm technology)
- Introduction to Joules
- Innovus 17.1 Topical Introduction
13:00 - 14:00
Lunch break
14:00 - 18:15Conference hall 3rd floor of the main lecture building
- Introduction to Stylus
- Physical verification with the help of PVS
- A new generation of verification software - Xcelium and Indago
- The history and future of megatrends in EDA
13 December 2017
9:00 - 18:00
Laboratory V-315 of the Department of Electronics
(Practical classes)
- Behavioral modeling
- Logical synthesis
- Simulation of a Verilog modules with element delays
- Physical design of the digital modules
- Verification of the digital modules
14 December 2017


10:00 - 12:00Laboratory V-315 of the Department of Electronics
- Working discussions, summarizing

Contact Event Secretary: E. Atkin
+7 495 7885699 ext. 9155
+7 499 3242597

Feb 16, 2015

Call for Papers [dvconeurope] DVCon-Europe 2015

 DVCON EUROPE 2015
The Design and Verification Conference & Exhibition Europe (DVCon Europe) is the premier conference for system architects, concept engineers, software developers, design and verification engineers, and IP integrators to share the latest methodologies and technologies on the practical use of EDA and IP languages and standards used in electronic design.

The focus of this highly technical conference is on the industrial application of specialized design and verification languages such as SystemC, SystemVerilog, VHDL, UVM or e; assertions in SVA or PSL; the use of AMS languages; design automation using IP-XACT; and the use of general purpose languages C and C++.

CALL FOR PAPERS
This call for papers solicits presentations that are highly technical and reflect real life experiences in using EDA languages, standards, methodologies and tools. Industry applications of interest include (but are not limited to) automotive, mobile communication, aerospace, healthcare, chip-cards, consumer and power electronics. Submissions are encouraged in (but not restricted to) the four topic areas listed below. Low power techniques and design for functional safety (e.g., ISO 26262, DO-254) are pervasive and can be addressed in any of these topics areas.

Please submit your draft version of the paper by May 1, 2015. Detailed instructions on the paper requirements and submission process can be found on www.dvcon-europe.org