Showing posts with label ULIS. Show all posts
Showing posts with label ULIS. Show all posts

Dec 20, 2018

[C4P] EuroSOI-ULIS April 1-3, 2019, Grenoble (F)

5th Joint International EUROSOI and ULIS Conference
at Minatec, Grenoble (F) 
on April 1-3, 2019

The Conference Committee hopes that you will actively participate by submitting high quality papers and will enjoy the conference. The Conference Technical Digest will be published by IEEE and will be available online through IEEE Xplore. The abstract submission deadline is January 15, 2019.

Invited Speakers:
  • Dr. Ionut RADU, SOITEC : "SOI technology: from niche to mainstream applications"
  • Dr. Anabela VELOSO, IMEC: "Nanowire for ultra-scaled, high-density logic and memory applications"
  • Dr. Marc GAILLARDIN, CEA: "Radiation effects in innovative devices"
  • Prof. Ru HUANG, Peking University: "Steep slope devices"
More information are provided in the attached 2nd C4P and on the Conference website

Dec 21, 2017

[call for papers] EUROSOI-ULIS2018, Granada

Joint International EUROSOI-ULIS Conference on SOI and Ultimate Integration on Silicon
Granada, Spain
on March 19-21, 2018

3rd Call for Papers 
Abstract Submission Deadline: January 12, 2018

The organizing committee invites scientists and engineers working in the above fields to actively participate by submitting high quality papers. Original 2-page abstracts with illustrations will be accepted for review in pdf format. The template is available at the conference website: congresos.ugr.es/eurosoi-ulis2018. The accepted abstracts will be published in a Proceedings book with an ISBN. The authors of the accepted contributions will be requested to provide a 4-page paper to appear in the conference proceedings, which will be submitted to the IEEE Xplore® digital library. A selection of the presented manuscripts in the conference will be invited to submit an extended version, which after a peer-review process, will be published as a Special Issue of Solid-State Electronics. A best paper award will be attributed to the best paper by the SINANO institute.

Papers in the following areas are solicited:
• Advanced SOI materials and wafers. Physical mechanisms and innovative SOI-like devices.
• New channel materials for CMOS: strained Si, strained SOI, SiGe, GeOI, III-V and high mobility materials on insulator; carbon nanotubes; graphene and other two-dimensional materials.
• Properties of ultra-thin films and buried oxides, defects, interface quality. Thin gate dielectrics: high-κ materials for switches and memory.
• Nanometer scale devices: technology, characterization techniques and evaluation metrics for high performance, low power, low standby power, high frequency and memory applications.
• Alternative transistor architectures including FDSOI, DGSOI, FinFET, MuGFET, vertical MOSFET, Nanowires, FeFET and Tunnel FET, MEMS/NEMS, Beyond-CMOS nanoelectronic devices.
• New functionalities in silicon-compatible nanostructures and innovative devices representing the More than Moore domain, nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, etc.
• CMOS scaling perspectives; device/circuit level performance evaluation; switches and memory scaling. Three-dimensional integration of devices and circuits, heterogeneous integration.
• Transport phenomena, compact modeling, device simulation, front- and back-end process simulation.
• Advanced test structures and characterization techniques, parameter extraction, reliability and variability assessment techniques for new materials and novel devices.
• Emerging memory devices

Invited Speakers:
• Prof. Jesús del Alamo (MIT, USA): III-V CMOS: Quo vadis?
• Prof. Hiroshi Iwai (TIT, Japan): 3D scaling of Si-IGBT.
• Prof. Enrique Calleja (Uni Madrid, Spain): MBE growth of ordered InGaN/GaN nano/microrods: basics and applications.
• Prof. Edward Yi Chang (NCTU, Taiwan): High performance GaN HEMT technologies.
• Prof. Adrian Ionescu (EPFL, Switzerland): Millivolt technology for low power digital and sensing applications.
• Dr. Byungil Kwak (SK Hynix, Korea): DRAM Peripheral Transistor Scaling using logic technologies – Future Challenges.

Jan 23, 2017

[EUROSOI ULIS] Deadline for abstract submission extended to January 29, 2017


Submit your abstract for  Conference to be held in Athens in April 2017 as soon as possible. We would like to inform you that, due to several requests, the deadline for abstract submission has been extended to January 29, 2017Please note that there will be both Oral and Poster Sessions 

Call for Papers

The organizing committee invites scientists and engineers working in the above fields to actively participate by submitting high quality papers. Original 2-page abstracts with illustrations will be accepted for review in pdf format. The accepted abstracts will be published in a Proceedings book with an ISBN. A 4-page follow-up paper delivered before will be published in IEEE Xplore Digital Library. The authors of the best papers will be invited to submit a longer version for publication in a special issue of Solid-State Electronics. A best paper award will be attributed to the best paper by the SINANO Institute. Both an Oral and a A Poster Session will be organized.

INVITED SPEAKERS
Prof. Maryline BawedinIMEP - INP Grenoble MINATEC, "The mystery of the Z2-FET 1T-DRAM memory"
Dr. Frank Schwierz, University of Ilmenau, "The Prospects of 2D Materials for Ultimately-Scaled CMOS"
Dr. Cosmin Roman, ETH Zurich, "Micro and Nano transducers for autonomous sensing applications"
Dr. Carlo Cagli,  CEA-LETI,  "Memories"
Dr. Anda Mocuta, IMEC, "Nanoscale FET"

The EUROSOI ULIS Conference Chairperson: 
Prof. Androula G. Nassiopoulou
NCSR Demokritos 
Athens, Greece