[C4P] 17th ITC at the University of Surrey

FIRST CALL FOR PAPER

The 17th International Thin-Film Transistor Conference (ITC2022) is dedicated to TFT related technologies for displays, sensors and general large area and flexible electronics. As TFT applications broaden and expand beyond traditional markets, the 17th ITC will provide a platform for sharing the research progress and discussing the challenges in this field. It will be between 14-16 September, hybrid format, online and on site at the University of Surrey (UK).

Areas of Interest include, but are not limited to:

• Semiconductor materials and processing for high performance TFTs
• Understanding and addressing instabilities of TFTs
• TFT based functional devices (e.g., sensors, memories, synapse)
• Scaling of TFTs for high resolution integration
• TFT compact models for circuit simulation
• TFT backplane integration for displays and sensors
• Flexible and stretchable TFT devices and circuits
• Circuit design and implementations of TFTs

Student Fee Waiver: Top student submissions will be awarded a full registration fee waiver (in person or online), supported by EPSRC Project ALPACA teamsporea.info/alpaca/. Visit the conference website for instructions on how to be considered

Important Dates:

• 17 May 2022 Two-page Abstract Submission Deadline
• 28 June 2022 Notification of Acceptance
• 19 July 2022 Registration Opens
• 14-16 September 2022 Conference dates

For further information, please visit: itc2022.net

[paper] Multi-Segment TFT Compact Model for THz Applications

Xueqing Liu¹,Trond Ytterdal² and Michael Shur^1,3

Multi-Segment TFT Compact Model for THz Applications

Nanomaterials 2022, 12(5), 765; 

DOI: 10.3390/nano12050765

  
1 RPI, Troy, NY 12180, USA
2 Norwegian University of Science and Technology, Trondheim, Norway
3 Electronics of the Future, Inc., USA

Abstract: We present an update of the Rensselaer Polytechnic Institute (RPI) thin-film transistor (TFT) compact model. The updated model implemented in Simulation Program with Integrated Circuit Emphasis (SPICE) accounts for the gate voltage-dependent channel layer thickness, enables the accurate description of the direct current (DC) characteristics, and uses channel segmentation to allow for terahertz (THz) frequency simulations. The model introduces two subthreshold ideality factors to describe the control of the gate voltage on the channel layer and its effect on the drain-to-source current and the channel capacitance. The calculated field distribution in the channel is used to evaluate the channel segment parameters including the segment impedance, kinetic inductance, and gate-to-segment capacitances. Our approach reproduces the conventional RPI TFT model at low frequencies, fits the measured current–voltage characteristics with sufficient accuracy, and extends the RPI TFT model applications into the THz frequency range. Our calculations show that a single TFT or complementary TFTs could efficiently detect the sub-terahertz and terahertz radiation.

FIG: (a) quivalent circuit of the multi-segment SPICE model for TFT and
(b) equivalent circuit for each segment including leakage components

Acknowledgements: The work was supported by Office of Naval Research (N000141712976, Project Monitor Paul Maki).

[paper] Model for TFT Used in a CMOS Inverter Amplifier

Adelmo Ortiz-Conde^a, CarlosÁvila-Avendaño^b, Jesús A.Caraveo-Frescas^b, Manuel A.Quevedo-López^b and Francisco J.García-Sánchez^a

A polylogarithmic model for thin-film transistors used in a CMOS inverter amplifier

Solid-State Electronics

Volume 188, February 2022, 108218

DOI: 10.1016/j.sse.2021.108218

   
a Solid State Electronics Laboratory, Universidad Simón Bolívar, Caracas 1080, Venezuela
b Materials Science and Engineering Department, University of Texas at Dallas, Richardson, TX 75080, USA

Abstract: This article presents a generalization of a transregional polylogarithmic model, previously proposed for continuously describing the transfer characteristics of polycrystalline and amorphous Thin Film Transistors (TFTs) at all levels of inversion. The present generalization entails including the necessary drain voltage dependencies to be able to describe also the output characteristics. The model is tested by using it in the design and analysis of a CMOS inverter amplifier consisting of poly-Si n- and p-channel TFTs fabricated at low temperature and pressure. The transistors are biased below threshold so that the CMOS amplifier circuit operates in weak conduction, having in mind energy saving considerations. The validity of the proposed model has been ascertained by comparing model simulations to actual measured data from individual poly-Si TFTs and from the CMOS amplifier circuit. The simulations of the CMOS inverter amplifier are compared to the results obtained using look-up table-type simulations.

Fig: Normalized current with respect to its maximum value versus gate bias for two different values of drain bias (top). The curve for the higher drain bias (blue dash line) is shifted to the right of that for the lower drain bias (red continuous line), indicating that VT increases as VDS increases. The corresponding Y function versus gate bias (bottom) illustrates a similar increase of VT with VDS. 

Acknowledgment: The authors would like to thank the reviewers and the editor for their valuable work, which has led to a significant improvement in the quality of this article.

[paper] Coplanar OTFT

Blurred Electrode for Low Contact Resistance in Coplanar Organic Transistors

Xiaolin Ye, Xiaoli Zhao, Shuya Wang, Zhan Wei, Guangshuang Lv, Yahan Yang, Yanhong Tong, Qingxin Tang, and Yichun Liu

American Chemical Society; Nano; Dec.18, 2020

DOI: 10.1021/acsnano.0c08122

*Center for Advanced Optoelectronic Functional Materials Research, and Key Lab of UV-Emitting Materials and Technology of Ministry of Education, Northeast Normal University, 5268 Renmin Street, Changchun 130024, China

Abstract: Inefficient charge injection and transport across the electrode/semiconductor contact edge severely limits the device performance of coplanar organic thin-film transistors (OTFTs). To date, various approaches have been implemented to address the adverse contact problems of coplanar OTFTs. However, these approaches mainly focused on reducing the injection resistance and failed to effectively lower the access resistance. Here, we demonstrate a facile strategy by utilizing the blurring effect during the deposition of metal electrodes, to significantly reduce the access resistance. We find that the transition region formed by the blurring behavior can continuously tune the molecular packing and thin-film growth of organic semiconductors across the contact edge, as well as provide continuously distributed gap states for carrier tunnelling. Based on this versatile strategy, the fabricated dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT) coplanar OTFT shows a high field-effect mobility of 6.08 cm2 V–1 s–1 and a low contact resistance of 2.32 kΩ cm, comparable to the staggered OTFTs fabricated simultaneously. Our work addresses the crucial impediments for further reducing the contact resistance in coplanar OTFTs, which represents a significant step of contact injection engineering in organic devices.

Fig: Coplanar Organic Transistors (oTFTs)

[paper] TFT for Mixed Signal and Analog Computation

Eva Bestelink, Olivier de Sagazan, Lea Motte, Max Bateson, Benedikt Schultes, S. Ravi P. Silva,

and Radu A. Sporea

Versatile Thin‐Film Transistor with Independent Control of Charge Injection and Transport

for Mixed Signal and Analog Computation

Adv. Intell. Syst.. (2020) pp.1-9, DOI:10.1002/aisy.202000199 

Abstract: New materials and optimized fabrication techniques have led to steady evolution in large area electronics, yet significant advances come only with new approaches to fundamental device design. The multimodal thin-film transistor introduced here offers broad functionality resulting from separate control of charge injection and transport, essentially using distinct regions of the active material layer for two complementary device functions, and is material agnostic. The initial implementation uses mature processes to focus on the device’s fundamental benefits. A tenfold increase in switching speed, linear input–output dependence, and tolerance to process variations enable low-distortion amplifiers and signal converters with reduced complexity. Floating gate designs eliminate deleterious drain voltage coupling for superior analog memory or computing. This versatile device introduces major new opportunities for thin-film technologies, including compact circuits for integrated processing at the edge and energy-efficient analog computation.

Figure: Outcomes of separating control for injection and conduction shown via TCAD simulation. a) MMT transient response is much faster than conventional contact-controlled TFTs

b) A MMT with multiple, appropriately sized CG1 gates can function as a digital-to-analog converter (DAC) with CG2 providing an enabling, sampleand-hold (S/H) function. 

Acknowledgements: E.B. and R.A.S. contributed equally to this work. This work was partly supported through EPSRC grants EP/R511791/1 and EP/R028559/1 and Research Fellowship 10216/110 from the Royal Academy of Engineering of Great Britain. Device fabrication had been performed on the NanoRennes platform. The authors thank Dr. Brice Le Borgne for initial liaison and process discussions, Prof. John M. Shannon for on-going advisory meetings, Prof. Craig Underwood for reviewing the manuscript, Dr. David Cox and Mr. Mateus Gallucci Masteghin for assistance with the SEM images.

[paper] Wearable Energy Harvester

A Piezoelectric-Transducer-Biased 3-D Photosensitive Thin-Film Transistor

as a Dual-Mode Wearable Energy Harvester

Emad Iranmanesh¹, Weiwei Li^2,3, Ahmed Rasheed^2,3, and Kai Wang^2,3 (Member IEEE)

IEEE EDL, Vol. 41, No. 9, Sept. 2020

DOI: 10.1109/LED.2020.3009685

¹School of Electronics and Information Technology, Sun Yat-sen University, Guangzhou 510006, China.
²Guangdong Provincial Key Laboratory of Display Material and Technology, Sun Yat-sen University, Guangzhou 510006, China
³State Key Laboratory of Optoelectronic Materials and Technologies, School of Electronics and Information Technology, Sun Yat-Sen University, Guangzhou 510006, China

Abstract: This letter reports on a dual-mode wearable energy harvester that utilizes both piezoelectric and photoelectric effects. It integrates a piezoelectric transducer with a 3-D photosensitive dual-gate thin-film transistor (DGTFT) as a rectifier and a buffer. The energy conversion efficiency is enhanced by reducing the internal resistance of the 3-D photosensitive DGTFT upon light illumination. Such a dual-mode energy harvester is promising for wearable electronics.

Fig.: a) Schematic diagram of the proposed wearable dual-mode energy harvester formed by a polyvinylidene difluoride (PVDF) transducer integrated with a self-driven diode-connected 3-D photosensitive DGTFT as a buffer and a rectifier;  b) Equivalent circuit of the proposed dual-mode harvester.

Acknowlwgement: This work was supported by the Guangdong Innovative Research and Entrepreneurial Team Program under Grant 2014ZT05D340

[paper] TFT Compact Modeling

Arun Dev Dhar Dwivedi, Sushil Kumar Jain, Rajeev Dhar Dwivedi and Shubham Dadhich

Numerical Simulation and Compact Modeling 

of Thin Film Transistors for Future Flexible Electronics

Submitted: July 4th 2019Reviewed: October 28th 2019Published: June 10th 2020

DOI: 10.5772/intechopen.90301

Abstract: In this chapter, we present a finite element method (FEM)-based numerical device simulation of low-voltage DNTT-based organic thin film transistor (OTFT) by considering field-dependent mobility model and double-peak Gaussian density of states model. Device simulation model is able to reproduce output characteristics in linear and saturation region and transfer characteristics below and above threshold region. We also demonstrate an approach for compact modeling and compact model parameter extraction of organic thin film transistors (OTFTs) using universal organic TFT (UOTFT) model by comparing the compact modeling results with the experimental results. Results obtained from technology computer-aided design (TCAD) simulation and compact modeling are compared and contrasted with experimental results. Further we present simulations of voltage transfer characteristic (VTC) plot of polymer P-channel thin film transistor (PTFT)-based inverter to assess the compact model against simple logic circuit simulation using SmartSpice and Gateway.

Fig.: Schematic cross-sectional diagram of organic TFTs 

along with the chemical structure of SAM and organic semiconductor.

Acknowledgments: The authors are thankful to SERB, DST, Government of India, for the financial support under Early Career Research Award (ECRA) for Project No. ECR/2017/000179.

INFOS 2017 in Potsdam, Germany

20th Conference on “Insulating Films on Semiconductors” 

INFOS 2017

June 27th – 30th, 2017 in Potsdam, Germany

The INFOS conference is a prestigious biennial event which brings together electrical engineers, technologists, materials scientists, device physics and chemists from Europe and around the world to debate the latest development in thin insulating film technology and identify as well as address challenges ahead in this highly diversifying field [read more...]

Conference Topics:

• High-k dielectrics, metal gate materials and SiO2 for future scaling
• Gate stack materials for high mobility substrates (Ge, SiGe, GaN, III-V)
• Stacked dielectrics for non-volatile memory (flash, nc-Si)
• Dielectrics for resistive switching memories and spin memories
• Dielectrics for DRAM and MIM
• Low-k dielectrics
• Semiconductors on insulators
• Dielectrics for 2D materials, nanowires, 2D devices and carbon-based devices
• Surface cleaning technologies
• Physics and chemistry of dielectrics and defects
• Characterization techniques for dielectrics and interfaces
• Electrical reliability, leakage and modelling
• Modelling of atomic structure of dielectrics, interfaces and thin films
• Topological insulators
• Ferroelectrics and functional oxides
• Dielectrics and thin films for TFT, amorphous or organic devices and photovoltaics
• Dielectrics for photonics and sensing

CTFT 2012

4th International Workshop on Compact Thin-Film Transistor (TFT) Modeling for Circuit Simulation

This workshop will provide a forum for discussions and current practices on compact TFT modeling. The workshop is sponsored by IEEE EDS Compact Modeling Technical Committee in joint collaboration with Cambridge University. A partial list of the areas of interest includes:

• Physics of TFTs and operating principles
• Compact TFT device models for circuit simulation
• Model implementation and circuit analysis techniques
• Model parameter extraction techniques
• Applications of compact TFT models in emerging products
• Compact models for interconnects in active matrix flat panels

The workshop organizers:
Department of Engineering, University of Cambridge, Cambridge, UK
Technical School of Engineering, University Rovira i Virgili, Tarragona, Spain