[paper] SiC Power MOSFET SPICE modelling

Akbar Ghulam

Accurate & Complete behaviourial SPICE modelling 

of commercial SiC Power MOSFET OF 1200V, 75A

25th EuroSimE, Catania, Italy, 2024, pp. 1-4,

DOI: 10.1109/EuroSimE60745.2024.10491420

* UNIPA Palermo (IT)

Abstract: Silicon Carbide (SiC) is proved to be an excellent replacement for Silicon in high voltage and high frequency applications due to its electro-thermal properties. Since SiC power MOSFETs have only recently been more widely available commercially, accurate simulation models are immediately required to forecast device behavior and facilitate circuit designs. The goal of this paper is to develop an accurate LTSPICE model based on a modified Enz-Krumenacher-Vittoz (EKV), MOSFET model for a 1200V, 30mΩ & 75ASiC power MOSFET “SCTW100N120G2AG” provided by STMicroelectronics that is currently on the market. The modified EKV model outperforms the reduced quadratic model by describing MOSFET behavior over different zones which are weak, moderate, and strong inversion zones with only a single equation. A wide range of experimental data was used to build the model's parameters. To estimate device performance in high frequency switching applications, the model has been expanded to include package parasitic components that include parasitic capacitances. The model's static and transient properties were simulated, and the results were compared with those acquired from the actual device.

FIG: The SiC MOSFET's circuit schematic utilizing a modified EKV model

Acknowledgements: We would like to thank STMicroelectronics, as for completion of this study has been greatly aided by their participation and availability of relevant data.

[webinar] Open Source Silicon Landscape

Unveiling the Open Source Silicon Landscape: 

a cutting-edge approach for the European semiconductor industry

5 December 2023

Who should attend and why:

• Policymakers at the regional, national, and European level who want to strengthen their respective semiconductor ecosystem while collaborating and contributing to the Union’s industry as a whole
• Research and academia representatives who are interested in deepening their knowledge or discovering the potential of the Open Source Silicon landscape
• SMEs in the semiconductor industry who aim to expand and innovate their business by using a cutting-edge approach
• Start-ups that are eager to elevate their business to the next level by embracing vanguard strategies
• Citizen scientists and the general public who would like to have a better understanding of the new horizons in the semiconductor landscape
• Experts active in industrial development who are interested in integrating potential new approaches

Registration:

The event is free of charge, but registration is mandatory. Registrants will receive the link to access the event by email.

Agenda:

11:00 - 11:05	Welcome
11:05 - 11:10	Introducing Open Source Silicon
11:10 - 11:20	BACKGROUND Open source silicon between software and hardware Background
11:20 - 11:40	POLICY BRIEF PRESENTATION Open source silicon’s position in the semiconductor value chain
11:40 - 12:35	PANEL Key opportunities and threats relevant to open source silicon strategies
12:35 - 12:45	Q&A and conclusions

[Workshop] QIP

Silicon Quantum Information Processing (QIP) Workshop

Glasgow Marriott Hotel

Wednesday, Sept. 20, 2023

Silicon Quantum Information Processing (QIP) is highly appealing due to excellent spin qubit performances and the expertise of the integrated circuit industry in device scaling. Demonstrations of long-lived, high-fidelity silicon qubits, multi-qubit gates and spin–photon coupling, are promising for the control and interconnect of QIP architectures. Recently, spin qubits in related semiconductors (e.g. germanium) have also emerged as promising implementations of scalable quantum hardware. The formidable challenge of scaling these systems to the level required for meaningful computational applications has also brought to the fore the need for robust cryo-CMOS electronics, which will enable fast control and data processing, as well as schemes to correct errors and protect against decoherence. This meeting will bring together leading researchers from the QIP communities of silicon and related semiconductors, as well as cryo-CMOS designers and engineers who are working at different layers of the “quantum stack”.

10:00AM- 10:10AM	Introduction
10:10AM- 10:40AM	Pablo Cova Farina Quantum dot ladders for quantum computation and simulation
10:40AM-11:00AM	Federico Fedele Automatic techniques for fast and automatic all-rf tuning of quantum devices
11:00AM-11:30AM	Mark Johnson Rapid characterisation of over 1000 silicon quantum dots
11:30AM-11:50AM	Break and refreshments
11:50AM-12:20PM	Gian Salis How are hole-spin qubits in Ge/SiGe heterostructures driven and why do they decohere?
12:20PM-12:40PM	Ross Leon Exchange control in a MOS double quantum dot made on a 300mm process
12:40PM-1:10PM	Asen Asenov A Methodology for Cryogenic PDK Re-Centering Using Experimental Data and TCAD Simulations
1:10PM-2:30PM	Lunch
2:30PM-3:00PM	Masoud Babaie A Cryo-CMOS Receiver for Spin Qubit Gate-Based Readout: from Modelling to Implementation and Verification
3:00PM-3:20PM	Mathieu de Krujif Measurement of classical electronics heating a local quantum dot thermometer in silicon
3:20PM-3:40PM	Janne Lehtinen Custom CMOS platform for quantum processor units
3:40PM-4:00PM	Stavroula Kapoulea Towards the Development of Quantum Computing System-On-Chip: Bringing Electronics Closer to Qubits
4:00PM-4:10PM	Concluding remarks
4:10PM-5:00PM	Refreshments
5:00PM-6:00PM	Lab tour
7:00PM-9:00PM	Conference Dinner

[paper] ULTRARAM Memory on Silicon

Peter D. Hodgson, Dominic Lane, Peter J. Carrington, Evangelia Delli, 

Richard Beanland and Manus Hayne

ULTRARAM: A Low-Energy, High-Endurance, Compound-Semiconductor Memory 

on Silicon

First published: 05 January 2022

Adv. Electron. Mater. 2022, 8, 2101103

DOI: 10.1002/aelm.202101103

Abstract: ULTRARAM is a nonvolatile memory with the potential to achieve fast, ultralow-energy electron storage in a floating gate accessed through a triple-barrier resonant tunneling heterostructure. Here its implementation is reported on a Si substrate; a vital step toward cost-effective mass production. Sample growth using molecular beam epitaxy commences with deposition of an AlSb nucleation layer to seed the growth of a GaSb buffer layer, followed by the III–V memory epilayers. Fabricated single-cell memories show clear 0/1 logic-state contrast after ≤10ms duration program/erase pulses of ≈2.5V, a remarkably fast switching speed for 10 and 20µm devices. Furthermore, the combination of low voltage and small device capacitance per unit area results in a switching energy that is orders of magnitude lower than dynamic random access memory and flash, for a given cell size. Extended testing of devices reveals retention in excess of 1000 years and degradation-free endurance of over 107 program/erase cycles, surpassing very recent results for similar devices on GaAs substrates.

FIG: a) Schematic cross-section of ULTRARAM device concept with corresponding material layers. The floating gate (1: FG), triple-barrier resonant-tunneling structure (2: TBRT), and readout channel (3) are highlighted. Arrows indicate the direction of electron flow during program/erase operations; b) Scanning electron micrograph of a fabricated device of 10 µm gate length. 

Acknowledgements: P.D.H. and D.L. contributed equally to this work. This work was supported by the Engineering and Physical Sciences Research Council, UK, via the 2017–2020 Impact Acceleration Account funding allocation to Lancaster University under grant EP/R511560/1, a scholarship under grant EP/N509504/1, equipment funding under grant EP/T023260/1, and the Future Compound Semiconductor Manufacturing Hub grant EP/P006973/1, by the ATTRACT project funded by the EC under Grant Agreement 777222 and by the Joy Welch Educational Charitable Trust.

[paper] Compound-Semiconductor Memory on Silicon

Peter D. Hodgson, Dominic Lane, Peter J. Carrington, Evangelia Delli,
Richard Beanland, and Manus Hayne

ULTRARAM: A Low-Energy, High-Endurance, 

Compound-Semiconductor Memory on Silicon 

Adv. Electron. Mater. 2022, 2101103

DOI: 10.1002/aelm.202101103

  
Department of Physics, University of Warwick (UK)

Abstract: ULTRARAM is a nonvolatile memory with the potential to achieve fast, ultralow-energy electron storage in a floating gate accessed through a triple-barrier resonant tunneling heterostructure. Here its implementation is reported on a Si substrate; a vital step toward cost-effective mass production. Sample growth using molecular beam epitaxy commences with deposition of an AlSb nucleation layer to seed the growth of a GaSb buffer layer, followed by the III–V memory epilayers. Fabricated single-cell memories show clear 0/1 logic-state contrast after ≤10 ms duration program/erase pulses of ≈2.5 V, a remarkably fast switching speed for 10 and 20 µm devices. Furthermore, the combination of low voltage and small device capacitance per unit area results in a switching energy that is orders of magnitude lower than dynamic random access memory and flash, for a given cell size. Extended testing of devices reveals retention in excess of 1000 years and degradation-free endurance of over 107 program/erase cycles, surpassing very recent results for similar devices on GaAs substrates.

Fig: ULTRARAM device concept. a) Schematic cross-section of a device with corresponding material layers. The floating gate (FG), triple-barrier resonant-tunneling structure (TBRT), and readout channel are highlighted. Arrows indicate the direction of electron flow during program/ erase operations. b) Scanning electron micrograph of a fabricated device of 10 µm gate length. 

Acknowledgements: P.D.H. and D.L. contributed equally to this work. This work was supported by the Engineering and Physical Sciences Research Council, UK, via the 2017–2020 Impact Acceleration Account funding allocation to Lancaster University under grant EP/R511560/1, a scholarship under grant EP/N509504/1, equipment funding under grant EP/T023260/1, and the Future Compound Semiconductor Manufacturing Hub grant EP/P006973/1, by the ATTRACT project funded by the EC under Grant Agreement 777222 and by the Joy Welch Educational Charitable Trust.

Neurotransistor MatLab Code

Eunhye Baek, Nikhil Ranjan Das, Carlo Vittorio Cannistraci, Taiuk Rim, Gilbert Santiago Cañón Bermúdez, Khrystyna Nych, Hyeonsu Cho, Kihyun Kim, Chang-Ki Baek, Denys Makarov, Ronald Tetzlaff, Leon Chua, Larysa Baraban and Gianaurelio Cuniberti

Intrinsic plasticity of silicon nanowire neurotransistors for dynamic memory and learning functions

Nat Electron (2020). 

DOI: 10.1038/s41928-020-0412-1

Abstract: Neuromorphic architectures merge learning and memory functions within a single unit cell and in a neuron-like fashion. Research in the field has been mainly focused on the plasticity of artificial synapses. However, the intrinsic plasticity of the neuronal membrane is also important in the implementation of neuromorphic information processing. Here we report a neurotransistor made from a silicon nanowire transistor coated by an ion-doped sol–gel silicate film that can emulate the intrinsic plasticity of the neuronal membrane. The neurotransistors are manufactured using a conventional complementary metal–oxide–semiconductor process on an 8-inch (200 mm) silicon-on-insulator wafer. Mobile ions allow the film to act as a pseudo-gate that generates memory and allows the neurotransistor to display plasticity. We show that multiple pulsed input signals of the neurotransistor are non-linearly processed by sigmoidal transformation into the output current, which resembles the functioning of a neuronal membrane. The output response is governed by the input signal history, which is stored as ionic states within the silicate film, and thereby provides the neurotransistor with learning capabilities.

FIG: Illustration of the structural similarity between the ion migration in the neurotransistor (left) and the membrane of a neuron cell in which the ionic current was modulated by a membrane potential (Vmemb) change in the case of the action potential (right)

Code availability: The MatLab code that supports the mathematical model in this article is available
at https://github.com/eunhye8747/MatLab-Code-Neurotransistor

Acknowledgements: This research was supported by the German Excellence Initiative via the Cluster of Excellence EXC1056 Center for Advancing Electronics Dresden (CfAED) and the MSIP (Ministry of Science, ICT and Future Planning), Korea, under the ICT Consilience Creative Program (IITP-R0346-16-1007) supervised by the IITP (Institute for Information & communications Technology Promotion). We acknowledge support from the Initiative and Networking Fund of the Helmholtz Association of German Research Centers through the International Helmholtz Research School for Nanoelectronic Networks (IHRS NANONET) (no. VH‐KO‐606) and German Research Foundation (DFG) via grants MA 5144/9-1, MA 5144/13-1 and MA 5144/14-1; BA4986/7−1, BA4986/8−1. Finally, we thank the INSA-DFG Bilateral Exchange Programme for financial support (IA/ DFG/2018/138, 12 April 2018). The authors thank S. Oswald (IFW Dresden) for the X-ray photoemission spectroscopy analysis of the ion-doped hybrid silicate films and M. Park (NamLab, Dresden) for the insightful discussion about the ionic polarization in the film. We thank R. Nigmetzianov (TU Dresden) for the film analysis.

[call for papers] EUROSOI-ULIS2018, Granada

Joint International EUROSOI-ULIS Conference on SOI and Ultimate Integration on Silicon

Granada, Spain

on March 19-21, 2018

3rd Call for Papers 

Abstract Submission Deadline: January 12, 2018

The organizing committee invites scientists and engineers working in the above fields to actively participate by submitting high quality papers. Original 2-page abstracts with illustrations will be accepted for review in pdf format. The template is available at the conference website: congresos.ugr.es/eurosoi-ulis2018. The accepted abstracts will be published in a Proceedings book with an ISBN. The authors of the accepted contributions will be requested to provide a 4-page paper to appear in the conference proceedings, which will be submitted to the IEEE Xplore® digital library. A selection of the presented manuscripts in the conference will be invited to submit an extended version, which after a peer-review process, will be published as a Special Issue of Solid-State Electronics. A best paper award will be attributed to the best paper by the SINANO institute.

Papers in the following areas are solicited:
• Advanced SOI materials and wafers. Physical mechanisms and innovative SOI-like devices.
• New channel materials for CMOS: strained Si, strained SOI, SiGe, GeOI, III-V and high mobility materials on insulator; carbon nanotubes; graphene and other two-dimensional materials.
• Properties of ultra-thin films and buried oxides, defects, interface quality. Thin gate dielectrics: high-κ materials for switches and memory.
• Nanometer scale devices: technology, characterization techniques and evaluation metrics for high performance, low power, low standby power, high frequency and memory applications.
• Alternative transistor architectures including FDSOI, DGSOI, FinFET, MuGFET, vertical MOSFET, Nanowires, FeFET and Tunnel FET, MEMS/NEMS, Beyond-CMOS nanoelectronic devices.
• New functionalities in silicon-compatible nanostructures and innovative devices representing the More than Moore domain, nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, etc.
• CMOS scaling perspectives; device/circuit level performance evaluation; switches and memory scaling. Three-dimensional integration of devices and circuits, heterogeneous integration.
• Transport phenomena, compact modeling, device simulation, front- and back-end process simulation.
• Advanced test structures and characterization techniques, parameter extraction, reliability and variability assessment techniques for new materials and novel devices.
• Emerging memory devices

Invited Speakers:
• Prof. Jesús del Alamo (MIT, USA): III-V CMOS: Quo vadis?
• Prof. Hiroshi Iwai (TIT, Japan): 3D scaling of Si-IGBT.
• Prof. Enrique Calleja (Uni Madrid, Spain): MBE growth of ordered InGaN/GaN nano/microrods: basics and applications.
• Prof. Edward Yi Chang (NCTU, Taiwan): High performance GaN HEMT technologies.
• Prof. Adrian Ionescu (EPFL, Switzerland): Millivolt technology for low power digital and sensing applications.
• Dr. Byungil Kwak (SK Hynix, Korea): DRAM Peripheral Transistor Scaling using logic technologies – Future Challenges.

[ESSCIRC 2015] Low-power analog RF circuit design based on the inversion coefficient

[ref] Enz, Christian; Chalkiadaki, Maria-Anna; Mangla, Anurag, "Low-power analog/RF circuit design based on the inversion coefficient," in ESSCIRC 2015 - 41st , vol., no., pp.202-208, 14-18 Sept. 2015

Abstract: This paper discusses the concept of the inversion coefficient as an essential design parameter that spans the entire range of operating points from weak via moderate to strong inversion, including velocity saturation. Several figures-of-merit based on the inversion coefficient, especially suitable for the design of low-power analog and RF circuits, are presented. These figures-of-merit incorporate the various trade-offs encountered in analog and RF circuit design. The use of the inversion coefficient and the derived figures-of-merit for optimization and design is demonstrated through simple examples. Finally, the simplicity of the inversion coefficient based analytical models is emphasized by their favorable comparison against measurements of a commercial 40-nm bulk CMOS process as well as with simulations using the BSIM6 model.

Keywords: Analytical models, Integrated circuits, Noise, Radio frequency, Silicon, Transconductance, Transistors, BSIM6

URL / doi: 10.1109/ESSCIRC.2015.7313863