[paper] Symmetric BSIM-SOI

Chetan Kumar Dabhi, Dinesh Rajasekharan, Girish Pahwa, Debashish Nandi, Naveen Karumuri, Sreenidhi Turuvekere, Anupam Dutta, Balaji Swaminathan, Srikanth Srihari, Yogesh S. Chauhan, Sayeef Salahuddin, and Chenming Hu

Symmetric BSIM-SOI: A Compact Model for Dynamically Depleted SOI MOSFETs 

 in IEEE TED (2024)

Part I DOI: 10.1109/TED.2024.3363110

Part II DOI: 10.1109/TED.2024.3363117

1 Department of Electrical Engineering and Computer Sciences, UCB, CA, USA

2 Department of Electrical Engineering, IIT Kanpur, India

3 GlobalFoundries, Bengaluru, India

Abstract: In this article, we present a symmetric surface-potential-based model for dynamic depletion (DD) device operation of silicon-on-insulator (SOI) FETs for RF and analog IC design applications. The model accurately captures the device behavior in partial depletion (PD) and full depletion (FD) modes, as well as in the transition from PD to FD, based on device geometry, doping, and bias conditions. The model also exhibits an excellent source–drain symmetry during dc and small-signal simulations, resulting in error-free higher order harmonics. The model is fully scalable with bias, temperature, and geometry and has been validated extensively with real device data from the industry. The symmetric BSIM-SOI model is developed in Verilog-A and compatible with all commercial SPICE simulators.

FIG: (a) Schematic of a typical SOI MOSFET

(b) Cgg versus Vgb for different substrate bias, with the PD-to-FD transition 

Acknowledgment: The authors thanks the members of the Compact Model Coalition (CMC), particularly Geoffrey J. Coram and Jushan Xie, for testing the model and suggesting improvements. The authors appreciate the CMC QA team’s efforts in conducting a model quality check. Caixia Han and Xiao Sun from Cadence provided a few useful test cases. They thank Ananth Sundaram and Anamika Singh Pratiyush from GlobalFoundries India for the help and discussion regarding DDSOI model intricacies and development. Model code is available at BSIM Website <https://bsim.berkeley.edu/models/bsimsoi/>

[paper] Noise Degradation and Recovery in Gamma-irradiated SOI nMOSFET

S.Amora^b, V.Kilchytska^a, F.Tounsi^a, N.André^a, M.Machhout^b, L.A.Francis^a, D.Flandre^a

Characteristics of noise degradation and recovery in gamma-irradiated SOI nMOSFET

with in-situ thermal annealing

Solid-State Electronics; 108300; online 7 April 2022, 

DOI: 10.1016/j.sse.2022.108300

   
a SMALL, ICTEAM Institute, Université catholique de Louvain (B)
b Faculté des Sciences de Université de Monastir (TN)

Abstract: This paper demonstrates a procedure for complete in-situ recovery of on-membrane CMOS devices from total ionizing dose (TID) defects induced by gamma radiation. Several annealing steps were applied using an integrated micro-heater with a maximum temperature of 365°C. The electrical characteristics of the on-membrane nMOSFET are recorded prior and during irradiation (up to 348 krad (Si)), as well as after each step of the in-situ thermal annealing. High-resolution current sampling measurements reveal the presence of oxide defects after irradiation, with a clear dominant single-trap signature in the random telegraph noise (RTN) traces. Drain current over time measurements are used for the trap identification and further for the defects' parameters extraction. The power spectral density (PSD) curves confirm a clear dominance of the RTN behavior in the low-frequency noise. A radiation-induced oxide trap is detected at 5.4 nm from the Si-SiO2 interface, with an energy of 0.086 eV from the Fermi level in the bandgap. After annealing, the RTN behavior vanishes with a further important reduction of flicker noise. Low-frequency noise measurements of the transistor confirmed the neutralization of oxide defects after annealing. The electro-thermal annealing of the nMOSFET allows a total recovery of its original characteristics after being severely degraded by radiation-induced defects.

Fig: Device under test : (a) cross-section schematic, (b) microscopic front view

showing the membrane and other embedded elements

[paper] Electron Mobility Distribution in FD-SOI MOSFETs

Nima Dehdashti Akhavan^a, Gilberto Antonio Umana-Membreno^a, Renjie Gu^a, Jarek Antoszewski^a, Lorenzo Faraone^a and Sorin Cristoloveanu^b

Electron mobility distribution in FD-SOI MOSFETs using a NEGF-Poisson approach

Solid-State Electronics; Available online 14 March 2022, 108283

DOI: 10.1016/j.sse.2022.108283

   
a The University of Western Australia, Crawley (AU)
b IMEP-LAHC, INP Minatec, Grenoble (F)

Abstract: Modern electronic devices consist of several semiconductor layers, where each layer exhibits a unique carrier transport properties that can be represented by a unique mobility characteristic. To date, the mobility spectrum analysis technique is the main approach that has been developed and applied to the analysis of conductivity mechanisms of multi-carrier semiconductor structures and devices. Currently, there are no theoretical calculations of the mobility distribution in semiconductor structures or devices and specifically in MOSFET devices. In this article, we present a theoretical study of the electron mobility distribution in planar fully-depleted silicon-on-insulator (FD-SOI) transistors employing quantum mechanical modelling. The simulation results indicate that electronic transport in the 10 nm thick Si channel layer at room-temperature is due to two distinct and well-defined electron species for channel length varying from 50 nm to 200 nm. The two electron mobility distributions provide clear evidence of sub-band modulated transport in 10-nm thick Si planar FD-SOI MOSFETs that are associated with primed and non-primed valleys of silicon. The potential of the top gate electrode has been modulated, and thus only the top channel inversion-layer electron population transport parameters have been investigated employing self-consistent non-equilibrium Green’s function (NEGF)–Poisson numerical calculations. The numerical framework presented can be used to interpret experimental results obtained by magnetic-field dependent geometrical magnetoresistance measurements and mobility spectrum analysis, and provides greater insight into electron mobility distributions in nanostructured FET devices.

Fig: Qinv is defined as the electron density per unit length at the maximum 

of the first subband (top of the barrier) often referred to as a “virtual source”

Acknowledgements: This work was supported by the Australian Research Council (DP170104555), the Horizon 2020 ASCENT EU project (Access to European Nanoelectronics Network – Project no. 654384), the Western Australian node of the Australian National Fabrication Facility (ANFF), and the Western Australian Government’s Department of Jobs, Tourism, Science and Innovation.

[paper] Embedded CMOS SOI UV Sensors

Michael Yampolsky, Evgeny Pikhay and Yakov Roizin

Embedded UV Sensors in CMOS SOI Technology

Sensors 2022, 22(3), 712;

DOI: 10.3390/s22030712

   
Tower Semiconductor, Migdal Haemek 2310502, Israel

Abstract: We report on ultraviolet (UV) sensors employing high voltage PIN lateral photodiode strings integrated into the production RF SOI (silicon on isolator) CMOS platform. The sensors were optimized for applications that require measurements of short wavelength ultraviolet (UVC) radiation under strong visible and near-infrared lights, such as UV used for sterilization purposes, e.g., COVID-19 disinfection. Responsivity above 0.1 A/W in the UVC range was achieved, and improved blindness to visible and infrared (IR) light demonstrated by implementing back-end dielectric layers transparent to the UV, in combination with differential sensing circuits with polysilicon UV filters. Degradation of the developed sensors under short wavelength UV was investigated and design and operation regimes allowing decreased degradation were discussed. Compared with other embedded solutions, the current design is implemented in a mass-production CMOS SOI technology, without additional masks, and has high sensitivity in UVC.

Fig: (a) A string of PIN photodiodes connected in series by silicide N+, P+, and iSi regions. The diodes are connected by butted silicide. The schematic cross section shows only three connected in series PIN diodes. (b) Cross section of a lateral PIN diode with contacts.

[paper] A Review of Sharp-Switching Band-Modulation Devices

Sorin Cristoloveanu¹, Joris Lacord², Sébastien Martinie², Carlos Navarro³, Francisco Gamiz³, Jing Wan⁴, Hassan El Dirani¹, Kyunghwa Lee¹ and Alexander Zaslavsky⁵

A Review of Sharp-Switching Band-Modulation Devices

Micromachines 2021, 12, 1540.

DOI: 10.3390/mi12121540

   
1 IMEP-LAHC, Université Grenoble Alpes (F)
2 CEA, LETI, MINATEC Campus (F)
3 CITIC-UGR, University of Granada (SP)
4 Fudan University, Shanghai (CN)
5 Brown University, Providence (US)

Abstract: This paper reviews the recently-developed class of band-modulation devices, born from the recent progress in fully-depleted silicon-on-insulator (FD-SOI) and other ultrathin-body technologies, which have enabled the concept of gate-controlled electrostatic doping. In a lateral PIN diode, two additional gates can construct a reconfigurable PNPN structure with unrivalled sharp-switching capability. We describe the implementation, operation, and various applications of these band-modulation devices. Physical and compact models are presented to explain the output and transfer characteristics in both steady-state and transient modes. Not only can band-modulation devices be used for quasi-vertical current switching, but they also show promise for compact capacitorless memories, electrostatic discharge (ESD) protection, sensing, and reconfigurable circuits, while retaining full compatibility with modern silicon processing and standard room-temperature low-voltage operation.

Fig: Average subthreshold swing SS vs. normalized ION plot. 

Green points indicate CMOS-compatible materials.

Acknowledgements: The European authors are grateful for support from the EU project REMINDER (H2020-687931). Alexander Zaslavsky acknowledges the support of the U.S. National Science Foundation (award QII-TACS-1936221).

[book] Fully Depleted SOI

Sorin Cristoloveanu; Fully Depleted Silicon-On-Insulator:

Nanodevices, Mechanisms and Characterization
2021 Elsevier B.V. 

ISBN: 978-0-12-819643-4

Fully Depleted Silicon-On-Insulator provides an in-depth presentation of the fundamental and pragmatic concepts of this increasingly important technology.

There are two main technologies in the marketplace of advanced CMOS circuits: FinFETs and fully depleted silicon-on-insulators (FD-SOI). The latter is unchallenged in the field of low-power, high-frequency, and Internet-of-Things (IoT) circuits. The topic is very timely at research and development levels. Compared to existing books on SOI materials and devices, this book covers exhaustively the FD-SOI domain. 

Key Features:

• Written by a top expert in the silicon-on-insulator community and IEEE Andrew Grove 2017 award recipient
• Comprehensively addresses the technology aspects, operation mechanisms and electrical characterization techniques for FD-SOI devices
• Discusses FD-SOI’s most promising device structures for memory, sensing and emerging applications

Table of Contents:

Front Matter

Preface

Part I: Technology

Chapter 1 - FD-SOI technology pp. 3-37

Part II: Mechanisms in FD-SOI MOSFET

Chapter 2 - Coupling effects pp. 41-70

Chapter 3 - Scaling effects pp. 71-114

Chapter 4 - Floating-body effects pp. 115-138

Part III: Electrical characterization techniques for FD-SOI structures

Chapter 5 - The pseudo-MOSFET pp. 141-177

Chapter 6 - Diode-based characterization methods pp. 179-200

Chapter 7 - Characterization methods for FD-SOI MOSFET pp. 201-238

Part IV: Innovative FD-SOI devices

Chapter 8 - Electrostatic doping and related devices pp. 241-265

Chapter 9 - Band-modulation devices pp. 267-298

Chapter 10 - Emerging devices pp. 299-348

FD-SOI teasers pp. 349-352

Index

[paper] 3D integrated GaN/RF-SOI SPST switch

Frédéric Drillet, Jérôme Loraine, Hassan Saleh, Imene Lahbib, Brice Grandchamp, Lucas Iogna-Prat, Insaf Lahbib, Ousmane Sow, Albert Kumar and Gregory U'Ren 

RF Small and large signal characterization of a 3D integrated GaN/RF-SOI SPST switch 

International Journal of Microwave and Wireless Technologies, pp. 1–6, 2021.

*X-FAB France, Corbeil-Essonnes (F)

Abstract: This paper presents the radio frequency (RF) measurements of an SPST switch realized in gallium nitride (GaN)/RF-SOI technology compared to its GaN/silicon (Si) equivalent. The samples are built with an innovative 3D heterogeneous integration technique. The RF switch transistors are GaN-based and the substrate is RF-SOI. The insertion loss obtained is below 0.4 dB up to 30 GHz while being 1 dB lower than its GaN/Si equivalent. This difference comes from the vertical capacitive coupling reduction of the transistor to the substrate. This reduction is estimated to 59% based on a RC network model fitted to S-parameters measurements. In large signal, the linearity study of the substrate through coplanar waveguide transmission line characterization shows the reduction of the average power level of H2 and H3 of 30 dB up to 38 dBm of input power. The large signal characterization of the SPST shows no compression up to 38 dBm and the H2 and H3 rejection levels at 38 dBm are respectively, 68 and 75 dBc.

Fig: X-FAB 3D integration proposal cross-section (left) and the picture of a GaN coupon (right).

Acknowledgement: We would like to acknowledge the Nano2022 program for partially funding this work.

Supplementary material: The supplementary material for this article can be found at DOI: 0.101/1759078721000076

[paper] Mobility in GC SOI Transistors

Lucas M. B. da Silva¹, Bruna Cardoso Paz², Michelly de Souza¹

Analysis of Mobility in Graded-Channel SOI Transistors Aiming at Circuit Simulation

Journal of Integrated Circuits and Systems; vol. 15, no. 2 pp.1-5 (2020) 

¹Department of Electrical Engineering, Centro Universitário FEI, São Bernardo do Campo, Brazil
²CEA, Leti, Grenoble, France

Abstract: This work presents an analysis of the behavior of the effective mobility of graded-channel FD SOI transistors using an Y-Function-based technique. Low field mobility, linear and quadratic attenuation factors were extracted from two-dimensional numerical simulations. The influence of the length of both channel regions over these parameters was analyzed. The parameters extracted from experimental data were used in a SPICE simulator, showing that it is possible to simulated GC SOI MOSFET using a regular SOI MOSFET model, by adjusting its parameters. This approach presents a percentage error smaller than 7.91% for low VDS.

Fig. Simulated curves of IDS vs. VGS and gm vs. VGS 

for GCSOI nMOSFETs with L= 2 µm and VDS=50 mV.

Acknowledgements: This study was supported by CNPq grants #311466/2016- 8 and #427975/2016-6. Authors would like to acknowledge Prof. Denis Flandre, from UCLouvain for providing the experimental samples.

[postponed]: EUROSOI-ULIS 2020

6th EUROSOI-ULIS

Caen, Normandy, France

The EUROSOI-ULIS organizers have announced that the conference 

and of the associated satellite events will be postponed to 

August 31st - September 4th

The sixth joint EUROSOI-ULIS conference will be hosted by Normandy University (ENSICAEN, UNICAEN, ESIGELEC) in Caen, inside the William the Conqueror Castel, in the auditorium of Museum of Fine Arts. The organizing committee invites scientists and engineers working on SOI technology and advanced nanoscale devices to actively participate by submitting high quality, original contributions (2-page abstracts).

The sixth joint EUROSOI-ULIS conference will be hosted by Normandy University (ENSICAEN, UNICAEN, ESIGELEC) in Caen, inside the William the Conqueror Castel, in the auditorium of Museum of Fine Arts. The organizing committee invites scientists and engineers working on SOI technology and advanced nanoscale devices to actively participate by submitting high quality, original contributions (2-page abstracts).

Important dates :

• abstract submission deadline : January 30, 2020
• notification of acceptance : February 3, 2020
• postponed confernce dates : August 31st - September 4th 2020

Papers in the following areas are solicited:
• Advanced SOI materials and structures: physical mechanisms and innovative SOI-like devices
• New channel materials for CMOS: strained Si, strained SOI, SiGe, GeOI, III-V and high mobility materials on insulator, carbon nanotubes, graphene and other two-dimensional materials
• Properties of ultra-thin films and buried oxides: defects, interface quality, thin gate dielectrics, high-κ materials for switches and memory.
• Nanometer scale devices: technology, characterization techniques and evaluation metrics for high performance, low power, reliability, high frequency and memory applications
• Alternative transistor architectures: FDSOI, Nanowire, FinFET, MuGFET, vertical MOSFET, FeFET and Tunnel FET, MEMS/NEMS, Beyond-CMOS nanoelectronic devices
• New functionalities in silicon-compatible nanostructures and innovative devices representing the More than Moore domain: nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, etc.
• CMOS scaling perspectives: device/circuit level performance evaluation, switches and memory scaling; three-dimensional integration of devices and circuits, heterogeneous integration
• Transport phenomena: compact modeling, device simulation, front- and back-end process simulation
• Advanced test structures and characterization techniques: parameter extraction, reliability and variability assessment techniques for new materials and novel devices

Need help or information : eurosoiulis2020@sciencesconf.org
Conference Chair: Bogdan Cretu