[paper] Effect of doping on Al2O3/GaN MOS capacitance

B.Rrustemi^ab, C.Piotrowicz^a, M-A.Jaud^a, F.Triozon^a, W.Vandendaele^a, B.Mohamad^a, R.Gwoziecki^a, G.Ghibaudo^b

Effect of doping on Al2O3/GaN MOS capacitance

Solid-State Electronics

Vol. 194, Aug. 2022, 108356

DOI: 10.1016/j.sse.2022.108356

   
a CEA, LETI, Grenoble (Fermi)
b IMEP-LAHC Minatec, Grenoble(FR)

Abstract: This paper investigates the turning-on-voltage (VFB/VTH) of Al2O3/GaN MOS stacks with n-doped GaN, p-doped GaN and not intentionally doped (NID) GaN by exploiting capacitance measurements on large gate area test structures with systematic variation of Al2O3 thickness (tox). Measurements are compared with 1D Schrödinger-Poisson simulations including incomplete ionization model. The necessity of using a quantum description of electron density is demonstrated especially for thinner gate oxides. We found that, contrary to what is expected, p-doping below the channel barely increases the VTH and the VTH is independent of tox, even if the density of activated acceptors is demonstrated to be sufficiently high. Our results highly suggest that the negative charge induced by p-doping is compensated at the oxide level.

Fig: Al2O3/GaN MOS stacks with n-doped GaN, p-doped GaN and its CV plots

[paper] Universal Charge Model for Multigate MOS Structures

Kwang-Woon Lee and Sung-Min Hong

Derivation of a Universal Charge Model for Multigate MOS Structures

with Arbitrary Cross Sections

IEEE TED (2022, Early Access)

DOI:  10.1109/TED.2022.316486

   

* Gwangju Institute of Science and Technology (KR)

Abstract: A universal equation for the charge-voltage characteristics in the multigate metal oxide semiconductor (MOS) structure with an arbitrary cross section is presented. A generalized coordinate is proposed and the Poisson equation is integrated with a weighting factor related with the generalized coordinate and the electric field. A compact charge model is derived and analytic and numerical examples for various MOS structures are shown.

Fig: Thin slab in the semiconductor channel region of the multigate MOS structure. The A∗ surfaces are perpendicular to the z-direction, which is the transport direction and its generalized coordinate, ψ, for rectangular nanosheet MOS structures at 0.0 V (top) and 0.7 V (bottom).

Aknowlegements: This workwas supported by the National Research Foundation of Korea (NRF) Grant funded by the Korean Government under Grant NRF- 2019R1A2C1086656 and Grant NRF-2020M3H4A3081800.

[papers] Compact/SPICE Modeling

[1] M. S. Tarkov; Two-Gate FeFET SPICE Model and Its Application to Construction of Adaptive Adder; 2021 Ural Symposium on Biomedical Engineering, Radioelectronics and Information Technology (USBEREIT), 2021, pp. 0206-0209,
DOI: 10.1109/USBEREIT51232.2021.9455091.

[2] L. Liu, Y. Tian and W. Huang, "A Bio-IA with Fast Recovery and Constant Bandwidth for Wearable Bio-Sensors," in IEEE Sensors Journal,
DOI: 10.1109/JSEN.2021.3092001.

[3] C. -T. Tung, H. -Y. Lin, S. -W. Chang and C. -H. Wu, "Analytical modeling of tunnel-junction transistor lasers," in IEEE Journal of Selected Topics in Quantum Electronics,
DOI: 10.1109/JSTQE.2021.3090527.

[4] Subir Kumar Maity, Soumya Pandit; A SPICE compatible physics-based intrinsic charge and capacitance model of InAs-OI-Si MOS transistor, Superlattices and Microstructures, Volume 156, 2021, 106975, ISSN 0749-6036,
DOI: 10.1016/j.spmi.2021.106975

Fig:  Strucutre of InAs-OI-Si MOS transistor

Program 2021: Symposium on Schottky Barrier MOS Devices

The symposium goal is to combine the activities of an enthusiastic group of Schottky barrier researchers worldwide. The topics cover all important aspects of potential applications, simulation and modeling, processing and implementation for CMOS/SOI technologies, Quantum technologies and approaches for neuromorphic applications. The content will be beneficial for anyone who needs to learn the opportunities and challenges of this technology since the first introduction by Walter Schottky in the 1938s. New aspects and future proposals to make the Schottky barrier into the main stream are welcome.

Program 2021

Wed 30.06.2021 (Virtual)

13:00-13:05	Opening IEEE DL
13:05-14:00	IEEE Distinguished Lecture: Tunneling Graphene FET Gana Nath Dash, Sambalpur University (IN) Abstract: During the last few decades, aggressive scaling in Si MOSFET (Metal Oxide Semiconductor Field Effect Transistor) architecture has given rise to several short channel effects, which in turn has set a performance limit on the device owing to constraint in Si technology. The emergence of graphene at this juncture with a host of exotic and favorable electronic properties, generated new hopes for the FET industry. While the graphene based analogue FET witnessed some advantages, the digital counterpart showed a dismal performance, primarily due to the zero bandgap of graphene (poor ON/OFF ratio). For a way out, an alternative architecture based on the quantum tunneling process is augmented with the graphene FET resulting in the new device named TGFET.
14:00-14:05	Opening SSBMOS
14:05-14:35	Germanium nanosheet and nanowire transistor technologies for beyond CMOS applications Walter M. Weber, Raphael Böckle, Lukas Wind, Kilian Eysin, Daniele Nazzari, Tatli Ezgi, Oliver Solfronk, Alois Lugstein and Masiar Sistani, Institute of Solid State Electronics, TU Vienna (A) Abstract: The ultimate downscaling limits of conventional field effect transistors calls for alternative computational methods that provide perspectives towards the enhancement of computational complexity, circuit performance and energy efficiency. In this sense germanium nano-transistors offer both an approachable access to quantum confinement effects and promising electronic transport properties that distinctly are compatible with modern CMOS fabrication flows. We will discuss the applicability of different germanium active regions and gating architectures towards the realization of computational electronics with added functionality. On top of exploring different realizations of reconfigurable transistors with programmable polarity we will discuss further functionality enhancement by enabling operability within the negative differential resistance regime at room temperature. Prospective implications at the circuit level will be discussed.
14:40-15:10	Evolving contact-controlled thin-film transistors Radu Sporea, University of Surrey (UK) Abstract: TFT designs that comprise multiple gates and rectifying source contacts can be designed to produce linear transconductance and act as robust amplifiers and signal converters. This talk outlines device design and opportunities in emerging edge processing applications.
15:10-15:50	COFFEE BREAK
15:50-16:20	Compact Modelling of Dually-Gated Reconfigurable Field-Effect Transistors Christian Römer*, Ghader Darbandy*, Mike Schwarz*, Jens Trommer**, André Heinzig**, Thomas Mikolajick**, Walter M. Weber***, Benjamín Iñíguez**** and Alexander Kloes* *NanoP, THM (DE), **namLAB, TU Dresden (DE), ***TU Vienna (A), ****DEEEA, URV (ES) Abstract: This work presents a closed-form and physics-based DC compact model, which is applicable on dually-gated reconfigurable field-effect transistors (RFETs). The presented compact model is focused on the charge-carrier injection at the device’s source and drain side Schottky barriers, which can be separated into field emission and thermionic emission current contributions. This work explains the basic equations which are used to calculate the current contributions and shows calculated device characteristics compared to measurements.
16:25-16:55	The Schottky barrier transistor in all its forms Laurie Calvet*, John P. Snyder**, Mike Schwarz*** *C2N, University Paris (FR),** JCap, LLC (USA), ***NanoP, THM (DE) Abstract: The Schottky barrier (SB) transistor, where the source and drain of a conventional planar MOSFET are replaced with metallic contacts, was first explored in the 1960s. Since then, many variations on this structure have been explored in the literature including: different semiconductors materials such as other non-organic semiconductors and nano-structures such as carbon nanotubes and nanowires. In this talk we review some of the changes in the electronic transport that are observed as the geometry and materials of the SB transistors are changed.

[RIP] prof. dr hab. inż. Andrzej Jakubowski

Professor Andrzej Jakubowski was born in 1940 in Kraków; died on March 9, 2021 in Warsaw. He was a graduate of the TU Warsaw. He obtained his PhD in 1974, and his habilitation (DSc) in 1983. Six years later, he was awarded the academic professor title. During his scientific and research carrier, he was the author or co-author of about 650 scientific papers, conference contributions and books (including [1]), 9 patents and patent applications, as well as promoting popular science. Professor Jakubowski was one of the most outstanding TU Warsaw professors, co-founder of the Polish microelectronics industry. He was also a pioneer of diamond-like and graphene layers application in microelectronics. For more than 50 years associated with the Institute of Microelectronics and Optoelectronics as its Director; founder of an outstanding scientific school of the micro and nanoelectronics, higly recognized in Poland as well as by many foreign R&D centers; a teacher and tutor of next generations of engineers; personally devoted to young people; with deep passion for half a century educating students and scientific staff at the highest international level with immense dedication of all his heart and scientific knowledge. Professor Jakubowski promoted 23 PhD students and may of them are working for international semiconductor companies and R&D organizations, now.

In the years 2004-2008 at the Warsaw University of Technology he was the director of the Institute of Microelectronics and Optoelectronics. Previously, he headed the Department of Microelectronics and the Department of Microelectronics and Nanoelectronics at this Institute. Between 1989 and 1992, he was the director of the Institute of Electron Technology (ITE, Warsaw; now Lukasiewicz IMiF). He was a member of the Electronics and Telecommunications Committee of the Polish Academy of Sciences. In 2014, Professor Jakubowski was awarded the honorary title of doctor honoris causa of TU Lodz. For his achievements in scientific and didactic work, he has received, among many others, the award of the Faculty of Technical Sciences of the Polish Academy of Sciences (PAN) and the Awards of the Minister of Science and Higher Education.

REF:
[1] Andrzej Jakubowski, Wieslaw Marciniak, Henryk M. Przewlocki; Diagnostic Measurements in LSI/VLSI Integrated Circuits Production; World Scientific, 30 Apr 1991; Technology & Engineering; 372pp

[paper] Simulations of transient processes in the nc-MOS structures

D. Tanous, A. Mazurak and B. Majkusiak 

Simulations of transient processes and characteristics of the nc-MOS structures 

Microelectronic Engineering, 

Volume 178, 2017, pp/ 173-177, 

DOI: 10.1016/j.mee.2017.05.013 

Abstract: Experimentally measured capacitance-voltage and current-voltage characteristics of the metal-insulator-semiconductor structures with nanocrystals embedded in the insulator often exhibit formations which result from charging/discharging processes of the nanocrystals and are difficult to explain and predict intuitively. Time dependent simulations as presented in this paper can be helpful in their analysis. The paper presents a study of the impact of selected geometrical parameters on their characteristics with the bias voltage ramp rate as a parameter.

FIG: a.) nc-MIS Structure; b.) Bias voltage ramp stimulation; c.)  CV and IV Simulations results

[PhD Thesis] III-V MOS-HEMTs for 100-340GHz Communications Systems

UNIVERSITY OF CALIFORNIA

Santa Barbara

III-V In_xGa_1-xAs / InP MOS-HEMTs for 100-340GHz Communications Systems

A dissertation for PhD degree in Electrical and Computer Engineering

by Brian David Markman

Abstract: This work summarizes the efforts made to extend the current gain cutoff frequency of InP based FET technologies beyond 1THz. Incorporation of a metal-oxide-semiconductor field effect transistor (MOSFET) at the intrinsic Gate Insulator-Channel interface of a standard high electron mobility transistor (HEMT) has enabled increased g_m,i by increasing the gate insulator capacitance density for a given gate current leakage density. Reduction of RS,TLM from 110 Ω.μm to 75Ω.μm and Ron(0) from 160Ω.μm to 120Ω.μm was achieved by removing/thinning the wide bandgap modulation doped link regions beneath the highly doped contact layers. Process repeatability was improved by developing a gate metal first process and D_it was improved by inclusion of a post-metal H₂ anneal. In_xGa_1-xAs / InAs composite quantum wells clad with both InP and In_xAl_1-xAs were developed for high charge density and low sheet resistance to minimize source resistance. 

Figure a) InP-based HEMT b) III-V DC optimized MOSFET c) proposed InP-based MOS-HEMT

---

[Citation] Markman, B. D. (2020). III-V In_xGa_1-xAs / InP MOS-HEMTs for 100-340GHz Communications Systems. UC Santa Barbara. ProQuest ID: Markman_ucsb_0035D_14853. Merritt ID: ark:/13030/m5v4681j. Retrieved from https://escholarship.org/uc/item/6st812pb

[paper] RESURF Model and Electrical Characteristics of Finger-Type STI Drain Extended MOS Transistors

RESURF Model and Electrical Characteristics of Finger-Type STI Drain Extended MOS Transistors
H. C. Tsai, R. H. Liou and C. Lien
IEEE Transactions on Electron Devices
vol. 63, no. 12, pp. 4603-4609, Dec. 2016

Abstract: Finger-type shallow trench isolation (finger STI) drain extended MOS transistors are fabricated and its electrical characteristics is studied. Polyplate on a finger STI served as a reduced surface field is adopted to enhance breakdown voltage (BV) by reducing the effective doping concentration of the drain extension (DE) finger. The conformal mapping method, which relates the reduction of the doping concentration to the width (z_o) of the DE finger, the gap (z_d) between the polyplate and the DE finger, and the STI depth (y_s), is used to estimate the reduction of the doping concentration theoretically. Based on this reduced doping concentration, a BV model is derived. The predictions of this model agree very well with the experimental data.

Keywords: Conformal mapping, Doping, Electric breakdown, MOS devices, Semiconductor process modeling, Silicon, Transistors, Drain extended MOS (DEMOS), Lateral double Diffused MOS (LDMOS), poly field plate, reduced surface field (RESURF)

doi: 10.1109/TED.2016.2605504
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