Showing posts with label IC. Show all posts
Showing posts with label IC. Show all posts

Mar 17, 2024

SSCS April Technical Webinar

SSCS April Technical Webinar


Abstract: In this presentation, Matt Venn will share his experience of getting started with chip design using the free and open source tools. Going from zero to 20 chips in 3 years, there are plenty of successes and failures to share. Matt will then move on to sharing the best resources, inspirational example projects, and showcase some of his own tools. The presentation will finish with a demonstration showing just how easy and cheap it is to get your own chip manufactured today.

Biography: Matt Venn is a science & technology communicator and electronic engineer. He has been involved with open source silicon for the last 3 years and has sent 20 chips for manufacture. He has helped over 600 people learn the tools, with 300 people taking part in manufacturable designs:
  • https://zerotoasiccourse.com/
  • https://tinytapeout.com
Date: 2024-04-19 Time: 11 AM ET
Location Webinar - Online
Contact Aeisha VanBuskirk – a.vanbuskirk@ieee.org

Register Here

Jan 29, 2024

Postdoc in Semiconductor Devices, and circuit design


Postdoc in Semiconductor Devices, and circuit design
Sønderborg, Denmark

We [sdu.dk] are seeking an enthusiastic new colleague as a PostDoc in the field of Semiconductor Devices, and circuit design. As a postdoc in our team, you will have the opportunity to contribute to cutting-edge research and innovation in this rapidly evolving field with a strong collaboration with international industry partners.

The position is located in the section of Electrical Engineering in Sønderborg within the Centre for Industrial Electronics (CIE). The Centre has currently approximately 30 faculty members including senior (full and associate professors), junior (assistant professors and postdocs), PhDs, and support staff. The task portfolio of the PostDocs will be linked to one main project and several smaller projects within CIE. CIE is embedded in a powerhouse in electronics, which includes researchers and developers at universities and industries on both sides of the Danish-German border. CIE is a new initiative striving for high quality and great impact of its research, innovation, and education. Central to achieving this objective is access to state-of-the-art facilities and collaborations with industries. In the semiconductor research group in CIE, we are a member of European projects and already settled our international collaborations with the pioneer industry.

The positions aim to build strong knowledge and competencies within the field of semiconductor devices, especially in the fields of wide band gap semiconductor devices, circuit design, failure mechanisms, and simulations.

Job description
  • Conduct research in the field of WBG semiconductors with a focus on GaN and SiC devices.
  • Innovate design structures through simulation-based approaches calibrated by experimental data.
  • Apply TCAD simulation and design tools, build demonstrators, and verify your simulation by experimental measurements.
  • Familiar with the fabrication process to realize devices in the clean room and explore their potential applications.
  • Experimental characterization of devices (static and dynamic) to analyze the device behavior.
  • Stay updated with the latest advancements in WBG semiconductor devices and contribute to the development of innovative solutions.
  • You will be involved in the daily supervision of PhD, Master, and Bachelor students who perform research on similar topics.
  • You will publish and present your work both at international conferences and in scientific journals with high impact.
Profile and requirements 
  • Ph.D. in Electrical Engineering, Semiconductor Physics, or a related field.
  • Strong background in theory and simulation of WBG semiconductor devices, device modeling, and circuit design.
  • Hands-on experience in fabrication processes such as lithography, Mask design, etching, and deposition appreciated.
  • Background in characterization techniques, failure mechanisms, and reliability tests.
  • Ability to work independently as well as collaboratively in a research team.
  • Strong communication skills to effectively present research findings and contribute to scientific discussions.
  • Ability to publish in high-impact conferences and journals.
Starting date: March 2024.
Type of contract: Full-time
Employment: 2-year position

Further information is available from 
Professor Thomas Ebel, Head of CIE, phone: +45 93 50 72 05 
Associate Professor Samaneh Sharbati, phone: +45 65 50 82 60

Conditions of employment

Employment as a postdoc requires scientific qualifications at PhD level. Employment as a postdoc is temporary and will cease without further notice at the end of the period. The successful applicant will be employed in accordance with the agreement between the Ministry of Finance and the Danish Confederation of Professional Associations

The assessment process

Read about the Assessment and selection process. Shortlisting may be used.

Application procedure
  • The application must be in English and must include:Motivated application
  • Detailed Curriculum Vitae
  • Certificates/Diplomas (MSc and PhD)
  • List of publications, indicating the publications attached
  • Examples of the most relevant publications. Please attach one pdf-file for each publication
  • Reference letters and other relevant qualifications may also be included.

Formalities
Documents should not contain a CPR number (civil registration number) – in this case, the CPR number must be crossed out. The application and CV must not exceed 10 MB. If you experience technical problems, you must contact hcm-support@sdu.dk.

The application deadline is 20. February 2024 at 23.59.

Further information for international applicants about entering and working in Denmark.

Further information about The Faculty of Engineering.

The University of Southern Denmark wishes to reflect the surrounding community and therefore encourages everyone, regardless of personal background, to apply for the position.


Jan 5, 2024

ISHI-kai January 2024 event

2024年1月イベント「オープンソースPDK団体」勉強会国内外のオ
ープンソースPDKやEDAの状況について、キーマンに語っていただきます
With the recent rise in the semiconductor industry, the movement of open source PDK and EDA in Japan and overseas has become active. Therefore, in this study session, key people will talk about the status of open source PDK and EDA in Japan and overseas.

Schedule
Friday, January 26, 2024, 18:00-21:00 (Reception: 18:30)

Venue (onsite)
Google Shibuya Office
3-21-3 Shibuya, Shibuya-ku, Tokyo
Shibuya Stream Google reception meeting

Online Broadcast: 
Google Meet: https://meet.google.com/ksa-tjaw-ges

Participation Fee
free
Timetable
TimeSpeakerTitleLecture Outline
Until 18:30ISHI-kaireceptionThe entrance to the facility closes at this time, so if you are participating locally, please come by this time as much as possible.
18:00 ~ 18:30ISHI-kaiChat time-
18:30 ~ 19:15 (Lecture: 30min, Q&A: 15min)Takeshi Hamamoto
Minimal Fab Propulsion Organization Device Engineer 
minimal Fab open PDK1) What is a minimal fab
2) openPDK
3) Design Contest at Semicon 2023

19:15 ~ 20:00 (Lecture: 30min., Q&A: 15min.)Junichi Okamura
IEEE Senior Member 
OpenPDK and the World-
20:00 ~ 20:45 (Lecture: 30min., Q&A: 15min.)@noritsunaAbout the upcoming open source PDK shuttle(To be released at a later date)
21:00ISHI-kaiclosing

What is ISHI-kai?
The association was named ISHI-kai (Inter-linked Society on Homemade IC Kai). The name was conceived from the Society Community (Association) that handles open (democratized) ISHI = stone = Silicon = semiconductors (ASIC/LSI/IC) and connects various fields.

OpenMPW (Open Multi Project Wafer), which appeared as a forerunner, is a shuttle program created by Google investing in Efabless, and includes the tools necessary for making semiconductors (ASIC/LSI/IC) (EDA/PDK) to ISHI manufacturing in IC fabs). This is exactly the "openness of semiconductors (ASIC/LSI/IC) and EDA/PDK" of the open source movement (democratization of software) that started with GNU!

Therefore, this association was established as a user society community (association) that focuses not only on experts in semiconductors (ASIC/LSI/IC) in the past, but also on those who see the potential of the open source movement of semiconductors (ASIC/LSI/IC) in the future and those who want to create new semiconductors (ASIC/LSI/IC).

We/ISHI-kai will continue to work toward a world where semiconductors (ASIC/LSI/IC) and EDA/PDK can be used by everyone, just as OSs, compilers, libraries, apps, electronic boards, 3D CAD and 3D printers that we/ISHI-kaire only available to experts can now be used by everyone as open source software, open hardware, open modeling, etc.

As for the future activity plan, we/ISHI-kai have a policy of revolutionizing the semiconductor (ASIC/LSI/IC) field by involving people from other fields, and we/ISHI-kai will hold events such as hands-on seminars for ultra-beginners for other fields and in-depth study sessions for experts, form a team to challenge the OpenMPW shuttle and Chipathon from around the world, and Maker we/ISHI-kai would like to participate in events such as Faire, so thank you.

Precautions
As events move online, we/ISHI-kai ask participants to act in accordance with the spirit of the Code of Conduct. If you have any problems, please contact the organizer. If it is judged that there is no improvement in the request even if there is no abuse such as vandalism or malicious intent, we/ISHI-kai may respond on a case-by-case basis. 
https://www.contributor-covenant.org/ja/version/2/0/code_of_conduct/

Acknowledgements
Thanks to the kindness of Google for providing a real/onsite venue.

Nov 10, 2023

Cutting-Edge IC Design Workshop

U.S. - Japan Collaboration Workshop
(Phase-1)
Tuesday, December 5 2023; 8:00 - 12:00 AM  (JST)
Wednesday, December 6 2023; 8:00 - 12:00 AM (JST) 
Online

The semiconductor industry is facing a number of challenges in building a stable supply chain. The importance of semiconductors was reaffirmed at the global level, and various initiatives were announced to revitalize and support the semiconductor industry, including investment in infrastructure development and human resource development for cutting-edge foundries. Against this backdrop, it is hoped that the creation of next-generation semiconductor technology and the further expansion of the industry will be achieved based on strong cooperation between Japan and the United States. As a phase 1 toward this goal, this workshop will discuss cutting-edge IC design technologies such as open source IC design, ecosystem construction, and human resource development. This workshop was supported by the U.S. Consulate in Fukuoka.

Application deadline is December 12. Please apply individually for DAY-1 and DAY-1the following form (you can also apply for only one of them).
[Participation fee] Free
[Notice] Simultaneous interpretation is available in English and at ZOOM Webinar.

DAY-1: Dec. 5th, 8:00-11:35 AM (JST)
8:00 - 8:05 Opening Remark and Overview of the Workshop, Mehdi Saligane, University of Michigan, Koji Inoue, Kyushu University
8:05 - 8:10 Welcome Remarks from the U.S. Consulate in Fukuoka
8:10 - 8:40 TBD, Steve Kosier, Skywater
8:40 - 9:10 The Emerging Ecosystem of Open-Source IC Design: IEEE SSCS Activities and Future Goals, Boris Murmann, Chair of the SSCS TC OSE, University of Hawaii
9:10 - 9:40 Human resource development for Semiconductor Technologies in Fukuoka, Koji Inoue, Fukuoka Semiconductor Reskilling Center/Kyushu University, Hideharu Kanaya, Kyushu University,
9:40 - 9:50 Break
9:50 - 10:20 Lab to Fab in the Cloud: Semiconductor Innovation at Amazon, David Pellerin, AWS 
10:20 - 10:50 TBD, Kai Yick, Google Research ML
10:50 - 11:20 Analog and Mixed-Signal IC Design Automation, David Wentzloff, University of Michigan
11:20 - 11:30 Q&A + Panel Discussion
11:30 - 11:35 Conclusion, Mehdi Saligane, University of Michigan

DAY-2: Dec. 6th, 8:00-11:30 AM (JST)
8:00 - 8:05 Opening Remark and Overview of the Workshop, Mehdi Saligane, University of Michigan, Koji Inoue, Kyushu University
8:05 - 8:35 Innovation by Collaboration: CHIPS Alliance, Rob Mains, CHIPS Alliance, Linux Foundation 
8:35 - 9:05 Developing CMOS+X Platforms for Artificial Intelligence and Beyond, Brian Hoskins, NIST 
9:05 - 9:35 Agile-X: Agile Chip Design and Fabrication Platform, Makoto Ikeda, University of Tokyo
9:35 - 9:45 Break
9:45 - 10:15 The future of semiconductor : chips and chiplets, Dan J. Dechene, IBM Research
10:15 - 10:45 AI Chip Design Center – open hub for chip innovation -, Kunio Uchiyama, National Institute of Advanced Industrial Science and Technology  
10:45 - 11:15 Democratizing EDA Tooling and Chip Design, Johan Euphrosine, Google (Tentative)
11:15 - 11:25 Q&A + Panel Discussion
11:25 - 11:30 Conclusion and Overview of the phase-2 workshop activities, Mehdi Saligane, University of Michigan, Koji Inoue, Kyushu University

[お問い合わせ] ic-design-ws 'at' slrc.kyushu-u.ac.jp ( 'at' を @ で置き換えてください)

Nov 3, 2023

The first IC designed in B&H has been fabricated

On 18 May 2023, the Faculty of Electrical Engineering of the University of Banja Luka, Bosnia and Herzegovina, presented the first integrated chip of semiconductor technology, which represents the most sophisticated technological process.

FIG: IC oscillates as per design specification and pre/post-layout simulation

Faculty of Electrical Engineering has become one of the higher education institutions where one of the most important engineering disciplines of today and the future is studied according to the best world programmes, with the direct application of industrial standards in teaching, thus preparing the next generation of engineers to be the flywheel of economic revival through innovation.
It took students and professors at the Faculty of Electrical Engineering five years to develop the first integrated chip. Student Vanja Žerić is one of the innovators of this idea, and he states that the knowledge gained was a prerequisite to start the production.
"We are talking about two chips, one of which is a stabilizer or a voltage regulator that has the ability to stabilize the voltage from 1.8 to 3.3 volts. The second was an oscillator that is essential for a chip like this.'', Vanja said.
Assistant Professor of the Faculty of Electrical Engineering, Aleksandar Pajkanović, PhD, who teaches several courses in the field of chip development at the Department of Electronics, pointed out that the CMOS technological process is the most sophisticated technology that exists in the world, and that it is commercially available, and that they have mastered it and demonstrated it through the implementation of the chip.
"It is particularly important to point out that this technology is significant as a military and industrial strategic resource as well as in higher education, and the most important thing is that we are now among world universities that study this field. It is usual for the implementation of chips to be done in doctoral studies, but with great efforts we managed to do it with third-year students. This chip is not intended for commercialization, as we developed it to demonstrate the capability and mastery of such advanced technology." Prof. Pajkanović stressed.

The details of that development are in the following references:

[1] A. Pajkanovic, “On the Application of Free CAD Software to Electronic Circuit Curricula”, 3rd IcETRAN2016, Zlatibor, Serbia, 2016
[2] A. Pajkanovic and Z. Ivanovic, “A Report on Recent Development in Application of Free CAD Software to IC Curricula,” 5th IcETRAN2018, Palic, Serbia, 2018.
[3] A. Pajkanovic, “Introducing Chisel to IC Design Curriculum at the Faculty of Electrical Engineering in Banja Luka”, 8th RISCV Workshop, Barcelona, Spain, 2018
[4] A. Pajkanovic, “CMOS IC Design from Schematic Level to Silicon within IC Curricula Using Free CAD Software”, INDEL2020, Banja Luka, B&H, 2020.
[5] A. Pajkanovic, “Free/Open Source EDA Tools Application in Digital IC Design Curricula”, 8th IcETRAN2021, Stanisici, B&H, 2021.
[7] A. Pajkanovic, "Free IC Design in Education", PSSOH 2021

[read more...]



 

Oct 26, 2023

[book] Microelectronic Circuits

Sedra, Adel S., Smith, Kenneth Carless, Carusone, 
Tony Chan, Gaudet, Vincent. 
Microelectronic Circuits. 
United Kingdom: Oxford University Press, 2020

Circuits by Sedra and Smith has served generations of electrical and computer engineering students as the best and most widely-used text for this required course. Respected equally as a textbook and reference, "Sedra/Smith" combines a thorough presentation of fundamentals with an introduction to present-day IC technology. It remains the best text for helping students progress from circuit analysis to circuit design, developing design skills and insights that are essential to successful practice in the field. Significantly revised with the input of two new coauthors, slimmed down, and updated with the latest innovations, Microelectronic Circuits, Eighth Edition, remains the gold standard in providing the most comprehensive, flexible, accurate, and design-oriented treatment of electronic circuits available today.


Appendix

  • B. SPICE Device Models and Design with Simulation Examples
Model files for representative CMOS technologies are provided below:

 

Jul 31, 2023

FOSS Circuit Simulators

AN OPEN-SOURCE, FREE CIRCUIT SIMULATOR
by: Bryan Cockfield on July 30, 2023

The original circuit simulation software, called the Simulation Program with Integrated Circuit Emphasis, or SPICE as it is more commonly known, was originally developed at the University of Califorina Berkeley in the 1970s with an open-source license. That’s the reason for the vast versions of SPICE available now decades after the original was released, not all of which are as open or free as we might like [1].

Fig: The Quite Universal Circuit Simulator includes a GUI based on the Qt toolkit and handles ad and ac analysis, S-parameters, harmonic balance analysis, noise analysis, and so forth. 

We’ve [2] listed all the simulators we found - the good, the bad, and the ugly - that actually did perform circuit simulation in some fashion. They are provided alphabetically, along with the most notable benefits and drawbacks we uncovered.


REF:
[1] An Open-Source, Free Circuit Simulator by Bryan Cockfield on July 30, 2023
[2] Best free analog circuit simulators by Lee Teschler on January 26, 2022

Jun 9, 2023

[Workshop] Open Source PDKs and EDA


RIHGA Royal Hotel Kyoto, Horikawa Shiokoji, Shimogyo ku, Kyoto 600 8237, Japan.
Date & Time: 5:30pm.-7:15pm on June 11 (Sun), 2023

Since its launch in 2020, the Open MPW shuttle program has received over 500 project submissions spanning 9 shuttles. This workshop will explore various topics related to designers' experiences, including measured results, foundry perspectives, and governmental expectations.

Organizers: 
  • Makoto Ikeda (The University of Tokyo)
  • Mehdi Saligane (University of Michigan)
Program:
  1. Design experience: “The Journey of Two Novice LSI Enthusiasts: Tape-Out of CPU+RAM in Just One Month”, Kazuhide Uchiyama, University of Electro-Communications and Yuki Azuma, University of Tsukuba
  2. From Zero to 1000 Open Source Custom Designs in Two Years, Mohamed Kassem, Co-founder and CTO, Efabless
  3. The SKY130 Open Source PDK: Building an Open Source Innovation Ecosystem, Steve Kosier, Skywater technology
  4. Open Source Chip Design on GF180MCU – A foundry perspective, Karthik Chandrasekaran, Global Foundries
  5. Japan Foundries' Perspectives on Silicon design democratization, Shiro Hara, Minimal Fab & AIST
  6. Google's perspective on Open source PDKs, Open source EDA tools, and OpenMPW shuttle program, Johan Euphrosine and Tim Ansell, Google
  7. The Nanofabrication Accelerator Project, Matthew Daniels, NIST
  8. Japanese government perspective on Silicon design democratization, Yohei Ogino, The Ministry of Economy, Trade and Industry METI
VLSI Symposium Workshop1 "Open Source PDKs and EDA" Audience


May 17, 2023

[chapter] Systematic Design of Analog CMOS Circuits with Lookup Tables

Systematic Design of Analog CMOS Circuits with Lookup Tables
By Paul G. A. Jespers, Université Catholique de Louvain, Belgium

in Foundations and Trends in Integrated Circuits and Systems
Vol. 2: No. 3, pp 193-243. http://dx.doi.org/10.1561/3500000004

Publication Date: 08 May 2023
© 2023 P. G. A. Jespers*

ABSTRACT The idea underlying the methodology described in this monograph consists in the use of a set of Lookup Tables embodying device data extracted prior from systematic runs done once and for all using an advanced circuit simulator, the same as used for final design verifications. In this way, all parameters put to use during the sizing procedure incorporate not only the bearings of bias conditions and geometry, but also every second-order effect present in the simulator’s model, in particular short-channel effects. Consequently, the number of verification simulations one has to perform is not only substantially reduced, but the designer may concentrate on actual design strategies without being bothered by inconsistencies caused by poor models or inappropriate parameters.

Fig: The drain current ID versus the gate-to-source voltage VGS (plain lines) compared to the EKV best fit (+). The other lines represent the exponential and quadratic approximations.

∗The author acknowledges the kind support of Prof. Boris Murmann in writing this monograph.

Apr 26, 2022

[paper] 50 Two-Transistor MOSFET Circuits

Harald Pretl* and Matthias Eberlein**
Fifty Nifty Variations of Two-Transistor Circuits: A tribute to the versatility of MOSFETs
IEEE Solid-State Circuits Magazine 13(3):38-46, August 2021
DOI: 10.1109/MSSC.2021.3088968  
  
* Institute for Integrated Circuits, JKU, Linz, Austria
** Semiconductor electronics, TU, Darmstadt, Germany


Abstract: We present a compendium of two-MOS-transistor circuits, spanning the range from simple standard configurations to ingenious arrangements. Using these building blocks, circuit designers can assemble a vast array of complex analog functions. This (incomplete) collection shall serve as a reference and inspiration to junior circuit designers and hopefully contains at least one unexpected example for the professional engineer.

Part 1/2 #thisismagic #circuit #mosfet


Part 2/2 #thisismagic #circuit #mosfet

Acknowledgments: We thank the reviewers for their many mindful suggestions. We want to thank our colleagues at the Institute for Integrated Circuits, Johannes Kepler University Linz, for their support in preparing this manuscript and for their many enlightening discussions.

Mar 2, 2022

[paper] SPICE Modeling and Circuit Demonstration of a SiC Power IC Technology

Tianshi Liu1, Hua Zhang1, Sundar Babu Isukapati2, Emran Ashik3, Adam J. Morgan2, Bongmook Lee3, Woongje Sung2, Ayman Fayed1, Marvin H. White1, and Anant K. Agarwal1
SPICE Modeling and Circuit Demonstration of a SiC Power IC Technology
IEEE Journal of the Electron Devices Society, vol. 10, pp. 129-138, 2022, 
DOI: 10.1109/JEDS.2022.315036
   
1 Department of Electrical & Computer Engineering, The Ohio State University, Columbus, OH 43210, USA
2 College of Nanoscale Science and Engineering, State University of New York Polytechnic Institute, Albany, NY 12309, USA
3 Department of Electrical & Computer Engineering, North Carolina State University, Raleigh, NC 27695, USA


Abstract: Silicon carbide (SiC) power integrated circuit (IC) technology allows monolithic integration of 600 V lateral SiC power MOSFETs and low-voltage SiC CMOS devices. It enables application-specific SiC ICs with high power output and work under harsh (high-temperature and radioactive) environments compared to Si power ICs. This work presents the device characteristics, SPICE modeling, and SiC CMOS circuit demonstrations of the first two lots of the proposed SiC power IC technology. Level 3 SPICE models are created for the high-voltage lateral power MOSFETs and low-voltage CMOS devices. SiC ICs, such as the SiC CMOS inverter and ring oscillator, have been designed, packaged, and characterized. Proper operations of the circuits are demonstrated. The effects of the trapped interface charges on the characteristics of SiC MOSFETs and SiC ICs are also discussed.
FIG: Cross-sectional view of the SiC MOSFETs (lot2)

Acknowledgment The authors would like to thank the team at Analog Devices (ADI), Hillview facility for the fabrication of devices and Advanced Research Projects Agency-Energy (ARPA-E). The authors also thank D. Xing for providing the customized gate driver for the dynamic characterizations of the circuits

Feb 2, 2022

[EZMod3D] Comparing inductance extraction to measurement

EZMod3D is a division of EASii IC, which develops a 3D multi-domain physical simulation software solution (also called 3D field solver) mainly developed to process the design of integrated circuits (ASICs), printed circuit boards (PCBs) and both at the same time (CoDesign). EZMod3D was developed on the basis of an innovative solver enabling a fast simulation. This technology has allowed intensive use internally at EASii IC, targeting the requirements of R&D project: reducing iterations between design and manufacturing.

Very simple, you just need to start with your input data
  • GDS2 file, OASIS database, LEF / DEF (ASIC) or Gerber (PCB) or DXF (Packaging)
  • Technological file or materials description
  • The position of the potentials or flows to be applied
  • In pre-sizing step, you can sketchup using advanced user intergrated matrial library
FIG: An inductor, its 3D EZMod3D simulation and LCR measurements. EZMod3D now extracts inductance values and shows good agreement with measurements.
Measured value is 477nH; close to the simulated 481nH)

Nov 27, 2021

[paper] Bridging the gap between design and simulation of low voltage CMOS circuits

C. M. Adornes, D. G. Alves Neto, M. C. Schneider and C. Galup-Montoro
Bridging the gap between design and simulation of low voltage CMOS circuits
2021 IEEE Nordic Circuits and Systems Conference (NorCAS), 2021, pp. 1-5,
DOI: 10.1109/NorCAS53631.2021.9599867

Abstract: This work proposes a simplified MOSFET model based on the Advanced Compact MOSFET (ACM) model, which contains only four parameters to assist the designer in understanding how the main MOSFET parameters affect the design. The 4-parameter model was implemented in Verilog-A to simulate different circuits designed with the ACM model. A CMOS inverter and a ring oscillator were designed and simulated, either using the 4-parameter ACM model or the BSIM model. The simulation results demonstrate that the 4-parameter model is very suitable for ultra-low-voltage (ULV) modeling. In the ultra-low-voltage domain, some of the secondary effects of the MOSFET are not relevant and thus not included in the 4-parameter model. A simplified MOSFET model for the ULV domain is of great importance to applications such as energy harvesting, sensor nodes for the Internet of Things, and always-on circuits.

Acknowledgment: The authors would like to thank the Brazilian agencies CAPES, finance code 001, and CNPq for supporting this work.

REF:
[1] A. I. A. Cunha, M. C. Schneider and C. Galup-Montoro, "An MOS Transistor Model for Analog Circuit Design", IEEE J. Solid-State Circuits, vol. 33, no. 10, pp. 1510-1519, October 1998
[2] C. Galup-Montoro and M. C. Schneider, "The compact all-region MOSFET model: theory and applications", IEEE 16th International New Circuits and Systems Conference (NEWCAS), pp. 166-169, June 2018
[3] M. C. Schneider and C. Galup-Montoro, CMOS Analog Design Using All-Region MOSFET Modeling, Cambridge University Press, 2010
[4] C. Galup-Montoro and M. C. Schneider, MOSFET modeling for circuit analysis and design, World Scientific, 2007
[5] Verilog-A Reference Manual, Agilent Technologies, 2004
[6] 0. F. Siebel, "Um modelo eficiente do transistor MOS para o projeto de circuitos VLSI," Universidade Federal de Santa Catarina, Florianopolis, 2007
[7] F. N. Fritsch, R. E. Shafer and W. P. Crowley, "Algorithm 443: Solution of the transcendental equation wew=x," Commun. ACM, vol. 16, no. 2, pp. 123-124, 1973
[8] O. F. Siebel, M. C. Schneider and C. Galup-Montoro, "MOSFET threshold voltage definition, extraction and some applications," Microelectronics Journal, vol. 43, no. 5, pp. 329-336, May 2012
[9] G. Hiblot. DIBL-Compensated Extraction of the Channel Length Modulation Coefficient in MOSFETS. IEEE Transactions on Electron Devices, vol. 65, no. 9, pp. 4015-4018, 2018
[10] BSIM4v4.5.0 Technical Manual, Department of Electrical Engineering and Computer Science, UC Berkeley, Berkeley, CA, USA. 2004
[11] Y. Tsividis and C. McAndrew, Operation and Modeling of the MOS Transistor, Oxford Univ. Press, 2011
[12] J. V. T. Ferreira, C. Galup-Montoro, "Ultra-low-voltage CMOS ring oscillators. Electronics Letters," IET, v. 55, n. 9, p. 523-525,2019
[13] E. M. Camacho-Galeano, C. Galup-Montoro and M. C. Schneider, "A 2-nW 1.1.-V self biased current reference in CMOS technology," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 52, no. 2, pp. 61-65, 2005
[14] E. Bolzan, E. B. Storck, M. C. Schneider and C. Galup-Montoro, "Design and testing of a CMOS SelfBiased Current Source," 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 382-385, 2019

Oct 26, 2021

conference paper reached 400 reads

conference paper reached 400 reads

Bucher, M., J-M. Sallese, F. Krummenacher, D. Kazazis, C. Lallement, W. Grabinski, and C. Enz
EKV 3.0: An analog design-oriented MOS transistor model
In 9th International Conference on Mixed Design of Integrated Circuits and Systems
(MIXDES 2002)

Abstract:  The EKV 3.0 compact MOS transistor model for advanced analog IC design and simulation is presented. The model is based on the surface potential approach combined with inversion charge linearization. The ideal long-channel model is coherent  for  static  and  dynamic  aspects  including  noise.  The  ideal  model  is  extended  for  high-field  effects  in  deep submicron CMOS technologies. Scalability over channel length and width is achieved while retaining a reduced number of parameters. The EKV 3.0 model is applicable over a large range of CMOS technologies.  

Fig: Normalized source transconductance to current ratio (gm/ID) vs. normalized current, measured 
(markers) in saturation from various CMOS technologies, and analytical model.


May 25, 2021

Circuit Design and Simulation Marathon using eSIM

 

Indian Institute of Technology, Bombay

We are happy to announce the first ever #Circuit #Design and #Simulation #Marathon using #eSim! This event is jointly organized by #FOSSEE and VLSI System Design. The FOSSEE project developed at Indian Institute of Technology, Bombay is powered by MINISTRY OF EDUCATION, GOVERNMENT OF INDIA.

To know more about the Circuit Design and Simulation Marathon, please visit https://hackathon.fossee.in/esim/

Important dates:
>> Registration: 21 May 2021 - 15 June 2021
>> Marathon Launch : 17 June 2021

May 18, 2021

[paper] Generalized Devices for SPICE Simulation of Soft Errors

Chiara Rossi, André Chatel and Jean-Michel Sallese*
Modeling Funneling Effect With Generalized Devices for SPICE Simulation of Soft Errors
in IEEE Transactions on Electron Devices,
doi: 10.1109/TED.2021.3076028 
* EPFL, 1015 Lausanne (CH)

Abstract: Recent advances in CMOS scaling have made circuits more and more sensitive to errors and dysfunction caused by ionizing radiation, even at ground level, requiring accurate modeling of such effects. Besides generation, transport, and collection of radiation-induced excess carriers, another phenomenon, called funneling, has to be modeled for an accurate prediction of soft errors. The funneling effect occurs when the radiation track crosses a space charge region and generates excess carriers with a density higher than the doping close to it. These carriers distort the electric field of the space charge region, deeply changing the transport mechanism, from diffusion in a field-free semiconductor to drift. The objective of this work is to include funneling as part of the generalized lumped devices model in order to obtain a complete tool for SPICE-compatible simulations of single-event effects (SEEs). The latter approach has been recently proposed to simulate radiation-induced charges in the silicon substrate and is based on the so-called generalized lumped devices that simulate charge generation, propagation, and collection using standard circuit simulators. The generalized devices are here extended to include funneling and used to simulate an alpha particle impinging on the bulk of nMOS and pMOS transistors. The results obtained are validated with TCAD numerical simulations. Finally, a static random-access memory (SRAM) struck by an alpha particle is analyzed. The model predicts that the occurrence of a soft error, i.e., flipping of memory state, may depend on whether or not there is funneling. This justifies the need for accurate modeling of funneling phenomena to predict SEEs in ICs.

FIG: Generalized devices network obtained for the pMOS substrate. The mesh is drawn in gray dashed lines. The network is not shown around the radiation track; only the mesh is reported, which is denser to linearize the generation profile and excess carrier gradients.

Aknowlwdgement: This work was supported by the Swiss National Science Foundation (NSF) under Grant 200021_165773.

Mar 17, 2021

[Workshop] Democratizing IC Design, April 7th, 2021

Solid-State Circuits Directions Workshop:
Democratizing IC Design
Wednesday, April 7th, 2021 at 7:00 AM PT / 10:00 AM ET
This event is free and open to all

EVENT DESCRIPTION
Solid-State Circuits Directions (SSCD) is a new technical committee within the IEEE Solid-State Circuits Society (related article). Its charter is to promote forward-looking topics, build new communities and stimulate interaction with others. Following SSCD’s inaugural event on hardware security, the upcoming workshop will look at the new movement toward an open-source ecosystem for integrated circuit design.

Over the past several decades, society has strongly benefited from free and open-source software. More recently, the open-source spirit has expanded to hardware and has energized a new maker community that tinkers with embedded systems at the printed circuit board level. Groundbreaking developments have now also opened the door toward democratizing integrated circuit design.

Last year, Google, SkyWater and efabless have partnered to launch a shuttle program based on SkyWater’s SKY130 open-source process (130 nm CMOS). This technology is offered to the open community along with a complete design flow to enable designers to implement their ideas. This workshop will provide an overview of this program and highlight upcoming opportunities to benefit from it. Finally, it will showcase specific design work delivered by the community members and articulate a call to action for volunteers to design, teach and mentor.

AGENDA
7:00 AM PT- Welcome & Introductions (Boris Murmann, Stanford University)
7:05 AM PT- Fully open source manufacturable PDK for a 130nm process (Tim Ansell, Google)
7:35 AM PT- 45 Chips in 30 Days: Open Source ASIC at its best! (Mohamed Kassem, efabless)
7:55 AM PT- Design 1: Open Source eFPGA implementation in SKY130 (Xifan Tang, University of Utah)
8:25 AM PT- Design 2: Amateur Radio Satellite Transceiver (Thomas Parry, SystematIC Design)
8:55 AM PT- Call to Action: Need volunteers to design, teach and mentor
9:00 AM PT- Adjourn

Feb 9, 2021

[paper] On-Chip Coplanar Waveguides

José Valdés-Rayón, Roberto S. Murphy-Arteaga and Reydezel Torres-Torres; 
Determination of the Contribution of the Ground-Shield Losses 
to the Microwave Performance of On-Chip Coplanar Waveguides 
IEEE Transactions on MTT; Feb.3, 2021 
DOI: 10.1109/TMTT.2021.3053548 
* National Institute of Astrophysics, Optics and Electronics (INAOE), Department of Electronics, Tonantzintla, Puebla 72840, Mexico.

Abstract: In this article, we characterize and model two parasitic effects that become apparent in the performance of coplanar waveguide interconnects in CMOS. One is the transverse resistance introduced by a patterned ground shield in coplanar waveguide interconnects, which significantly contributes to the shunt losses. The other one is the parasitic coupling between the input and output ports through the ground shield. The latter effect is particularly accentuated in relatively short lines and complicates the determination of the propagation constant using line-line algorithms at several tens of gigahertz. We demonstrate that using the proposed methodology, excellent model-experiment correlation can be achieved in the modeling of these types of interconnects up to at least 60 GHz.

Funding: CONACyT-Mexico

Jan 6, 2021

Virtual Si Museum /2101/ Electron Devices Time Line

my own view on the electron devices time line. The electron devices scaling: from a single vacuum tube, a BJT, TTL digital ICs to 68719476736 devices in a NAND flash memory card. If you have something else to add, just let me know:

REF:
  1. Vacuum Tube GE 9-22 188-5
  2. 2N2905A BJT - PNP, -60 V, -600 mA, 600 mW, TO-39
  3. TTL 74F00 IC - 5V, quad 2-input NAND gate; series F (=fast) introduced in 1978
  4. 64Gb NAND flash memory card

Oct 12, 2020

[chapter] Low-Voltage Analog IC Design

Deepika Gupta1
Low-Voltage Analog Integrated Circuit Design
Nanoscale VLSI. Book series (ESIEE) (2020) pp 3-22
DOI: 10.1007/978-981-15-7937-0_1
1Department of Electronics and Communication Engineering, IIIT Naya Raipur, India

Abstract: In this chapter, we review the challenges and effective design techniques for ultra-low-power analog integrated circuits. With the miniaturization, having low-power low-voltage mixed signal IC is essential to maintain the electric field in the device. This constraint presents bottleneck for the researchers to design robust analog circuits. Specifically, the low value of supply voltage with small technology influences many specifications of analog IC, e.g., power supply rejection, dynamic range and immunity to noise, etc. In addition, it also affects the ability of the MOS transistor to be operated in the strong inversion region. Note that with the technology reduction, power supply VDD is reducing but the threshold voltage VT is not decreasing proportionally to maintain low leakage current. However, this process reduces the overdrive voltage and limits the staking of transistors. In this case, the transistor can be made to work in weak inversion to work and reduce the power consumption. Further, reduction in VDD to achieve low-power consumption causes many other circuit-related issues such as PVT variations, degradation of dynamic range, mismatching in circuits element and differential paths. There have been many design methods developed for the ultra-low-power analog ICs. In this chapter, we will discuss some of the design techniques to reduce the power consumption in analog ICs. In addition, we will also discuss the basic building blocks of analog circuits with discussed design techniques. The charge-based EKV model can be a very suitable example of a MOS simulation model to be used in all inversion regions of transistor operations [Enz 2017]. In EKV model, the smallest number of core parameters is needed for the accurate behavioral modeling of transistor. Particularly, charge-based EKV model is beneficial for the analysis of analog circuits because it allows the analysis with simple calculations over different inversion regions. Hence, developing new device simulation models specific for analog circuit design is crucial.
Fig: Vth and Vdd scaling trend vs. Leff  [Zhao 2006]
References:
[Enz 2018] Enz C, Chicco F, Pezzotta A (2017) Nanoscale MOSFET modeling-part 1: the simplified EKV model for the design of low-power analog circuits. IEEE Solid-State Circuits Magazine 9(3):26–35
[Zhao 2006] Zhao W, Cao Y (2006) New generation of predictive technology model for sub-45 nm early design exploration. IEEE Trans Electron Devices 53(11):2816–2823