- https://zerotoasiccourse.com/
- https://tinytapeout.com
Mar 17, 2024
SSCS April Technical Webinar
Jan 29, 2024
Postdoc in Semiconductor Devices, and circuit design
Job description
- Conduct research in the field of WBG semiconductors with a focus on GaN and SiC devices.
- Innovate design structures through simulation-based approaches calibrated by experimental data.
- Apply TCAD simulation and design tools, build demonstrators, and verify your simulation by experimental measurements.
- Familiar with the fabrication process to realize devices in the clean room and explore their potential applications.
- Experimental characterization of devices (static and dynamic) to analyze the device behavior.
- Stay updated with the latest advancements in WBG semiconductor devices and contribute to the development of innovative solutions.
- You will be involved in the daily supervision of PhD, Master, and Bachelor students who perform research on similar topics.
- You will publish and present your work both at international conferences and in scientific journals with high impact.
- Ph.D. in Electrical Engineering, Semiconductor Physics, or a related field.
- Strong background in theory and simulation of WBG semiconductor devices, device modeling, and circuit design.
- Hands-on experience in fabrication processes such as lithography, Mask design, etching, and deposition appreciated.
- Background in characterization techniques, failure mechanisms, and reliability tests.
- Ability to work independently as well as collaboratively in a research team.
- Strong communication skills to effectively present research findings and contribute to scientific discussions.
- Ability to publish in high-impact conferences and journals.
Type of contract: Full-time
Employment: 2-year position
Further information is available from
Professor Thomas Ebel, Head of CIE, phone: +45 93 50 72 05
Associate Professor Samaneh Sharbati, phone: +45 65 50 82 60
Conditions of employment
Employment as a postdoc requires scientific qualifications at PhD level. Employment as a postdoc is temporary and will cease without further notice at the end of the period. The successful applicant will be employed in accordance with the agreement between the Ministry of Finance and the Danish Confederation of Professional Associations
The assessment process
Read about the Assessment and selection process. Shortlisting may be used.
Application procedure
- The application must be in English and must include:Motivated application
- Detailed Curriculum Vitae
- Certificates/Diplomas (MSc and PhD)
- List of publications, indicating the publications attached
- Examples of the most relevant publications. Please attach one pdf-file for each publication
- Reference letters and other relevant qualifications may also be included.
Formalities
Documents should not contain a CPR number (civil registration number) – in this case, the CPR number must be crossed out. The application and CV must not exceed 10 MB. If you experience technical problems, you must contact hcm-support@sdu.dk.
The application deadline is 20. February 2024 at 23.59.
Further information for international applicants about entering and working in Denmark.
Further information about The Faculty of Engineering.
Jan 5, 2024
ISHI-kai January 2024 event
ープンソースPDKやEDAの状況について、キーマンに語っていただきます
Schedule
Friday, January 26, 2024, 18:00-21:00 (Reception: 18:30)
Venue (onsite)
Google Shibuya Office
3-21-3 Shibuya, Shibuya-ku, Tokyo
Shibuya Stream Google reception meeting
Online Broadcast:
Google Meet: https://meet.google.com/ksa-tjaw-ges
Participation Fee
free
Time | Speaker | Title | Lecture Outline |
---|---|---|---|
Until 18:30 | ISHI-kai | reception | The entrance to the facility closes at this time, so if you are participating locally, please come by this time as much as possible. |
18:00 ~ 18:30 | ISHI-kai | Chat time | - |
18:30 ~ 19:15 (Lecture: 30min, Q&A: 15min) | Takeshi Hamamoto Minimal Fab Propulsion Organization Device Engineer | minimal Fab open PDK | 1) What is a minimal fab 2) openPDK 3) Design Contest at Semicon 2023 |
19:15 ~ 20:00 (Lecture: 30min., Q&A: 15min.) | Junichi Okamura IEEE Senior Member | OpenPDK and the World | - |
20:00 ~ 20:45 (Lecture: 30min., Q&A: 15min.) | @noritsuna | About the upcoming open source PDK shuttle | (To be released at a later date) |
21:00 | ISHI-kai | closing |
Nov 10, 2023
Cutting-Edge IC Design Workshop
(Phase-1)
Tuesday, December 5 2023; 8:00 - 12:00 AM (JST)
Wednesday, December 6 2023; 8:00 - 12:00 AM (JST)
Nov 3, 2023
The first IC designed in B&H has been fabricated
The details of that development are in the following references:
[1] A. Pajkanovic, “On the Application of Free CAD Software to Electronic Circuit Curricula”, 3rd IcETRAN2016, Zlatibor, Serbia, 2016[2] A. Pajkanovic and Z. Ivanovic, “A Report on Recent Development in Application of Free CAD Software to IC Curricula,” 5th IcETRAN2018, Palic, Serbia, 2018.[3] A. Pajkanovic, “Introducing Chisel to IC Design Curriculum at the Faculty of Electrical Engineering in Banja Luka”, 8th RISCV Workshop, Barcelona, Spain, 2018[4] A. Pajkanovic, “CMOS IC Design from Schematic Level to Silicon within IC Curricula Using Free CAD Software”, INDEL2020, Banja Luka, B&H, 2020.[5] A. Pajkanovic, “Free/Open Source EDA Tools Application in Digital IC Design Curricula”, 8th IcETRAN2021, Stanisici, B&H, 2021.[6] A. Pajkanovic, “Open Source CMOS General Purpose Operational Amplifier", MIEL 2021[7] A. Pajkanovic, "Free IC Design in Education", PSSOH 2021
Oct 26, 2023
[book] Microelectronic Circuits
Appendix
- B. SPICE Device Models and Design with Simulation Examples
Jul 31, 2023
FOSS Circuit Simulators
REF:
[1] An Open-Source, Free Circuit Simulator by Bryan Cockfield on July 30, 2023
[2] Best free analog circuit simulators by Lee Teschler on January 26, 2022
Jun 9, 2023
[Workshop] Open Source PDKs and EDA
- Makoto Ikeda (The University of Tokyo)
- Mehdi Saligane (University of Michigan)
- Design experience: “The Journey of Two Novice LSI Enthusiasts: Tape-Out of CPU+RAM in Just One Month”, Kazuhide Uchiyama, University of Electro-Communications and Yuki Azuma, University of Tsukuba
- From Zero to 1000 Open Source Custom Designs in Two Years, Mohamed Kassem, Co-founder and CTO, Efabless
- The SKY130 Open Source PDK: Building an Open Source Innovation Ecosystem, Steve Kosier, Skywater technology
- Open Source Chip Design on GF180MCU – A foundry perspective, Karthik Chandrasekaran, Global Foundries
- Japan Foundries' Perspectives on Silicon design democratization, Shiro Hara, Minimal Fab & AIST
- Google's perspective on Open source PDKs, Open source EDA tools, and OpenMPW shuttle program, Johan Euphrosine and Tim Ansell, Google
- The Nanofabrication Accelerator Project, Matthew Daniels, NIST
- Japanese government perspective on Silicon design democratization, Yohei Ogino, The Ministry of Economy, Trade and Industry METI
May 17, 2023
[chapter] Systematic Design of Analog CMOS Circuits with Lookup Tables
Apr 26, 2022
[paper] 50 Two-Transistor MOSFET Circuits
** Semiconductor electronics, TU, Darmstadt, Germany
Abstract: We present a compendium of two-MOS-transistor circuits, spanning the range from simple standard configurations to ingenious arrangements. Using these building blocks, circuit designers can assemble a vast array of complex analog functions. This (incomplete) collection shall serve as a reference and inspiration to junior circuit designers and hopefully contains at least one unexpected example for the professional engineer.
Part 1/2 #thisismagic #circuit #mosfet
Mar 2, 2022
[paper] SPICE Modeling and Circuit Demonstration of a SiC Power IC Technology
1 Department of Electrical & Computer Engineering, The Ohio State University, Columbus, OH 43210, USA
2 College of Nanoscale Science and Engineering, State University of New York Polytechnic Institute, Albany, NY 12309, USA
3 Department of Electrical & Computer Engineering, North Carolina State University, Raleigh, NC 27695, USA
Feb 2, 2022
[EZMod3D] Comparing inductance extraction to measurement
Very simple, you just need to start with your input data
- GDS2 file, OASIS database, LEF / DEF (ASIC) or Gerber (PCB) or DXF (Packaging)
- Technological file or materials description
- The position of the potentials or flows to be applied
- In pre-sizing step, you can sketchup using advanced user intergrated matrial library
Nov 27, 2021
[paper] Bridging the gap between design and simulation of low voltage CMOS circuits
Oct 26, 2021
conference paper reached 400 reads
May 25, 2021
Circuit Design and Simulation Marathon using eSIM
To know more about the Circuit Design and Simulation Marathon, please visit https://hackathon.fossee.in/esim/
Important dates:
>> Registration: 21 May 2021 - 15 June 2021
>> Marathon Launch : 17 June 2021
May 18, 2021
[paper] Generalized Devices for SPICE Simulation of Soft Errors
Abstract: Recent advances in CMOS scaling have made circuits more and more sensitive to errors and dysfunction caused by ionizing radiation, even at ground level, requiring accurate modeling of such effects. Besides generation, transport, and collection of radiation-induced excess carriers, another phenomenon, called funneling, has to be modeled for an accurate prediction of soft errors. The funneling effect occurs when the radiation track crosses a space charge region and generates excess carriers with a density higher than the doping close to it. These carriers distort the electric field of the space charge region, deeply changing the transport mechanism, from diffusion in a field-free semiconductor to drift. The objective of this work is to include funneling as part of the generalized lumped devices model in order to obtain a complete tool for SPICE-compatible simulations of single-event effects (SEEs). The latter approach has been recently proposed to simulate radiation-induced charges in the silicon substrate and is based on the so-called generalized lumped devices that simulate charge generation, propagation, and collection using standard circuit simulators. The generalized devices are here extended to include funneling and used to simulate an alpha particle impinging on the bulk of nMOS and pMOS transistors. The results obtained are validated with TCAD numerical simulations. Finally, a static random-access memory (SRAM) struck by an alpha particle is analyzed. The model predicts that the occurrence of a soft error, i.e., flipping of memory state, may depend on whether or not there is funneling. This justifies the need for accurate modeling of funneling phenomena to predict SEEs in ICs.
FIG: Generalized devices network obtained for the pMOS substrate. The mesh is drawn in gray dashed lines. The network is not shown around the radiation track; only the mesh is reported, which is denser to linearize the generation profile and excess carrier gradients.
Aknowlwdgement: This work was supported by the Swiss National Science Foundation (NSF) under Grant 200021_165773.
Mar 17, 2021
[Workshop] Democratizing IC Design, April 7th, 2021
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Feb 9, 2021
[paper] On-Chip Coplanar Waveguides
Jan 6, 2021
Virtual Si Museum /2101/ Electron Devices Time Line
my own view on the electron devices time line. The electron devices scaling: from a single vacuum tube, a BJT, TTL digital ICs to 68719476736 devices in a NAND flash memory card. If you have something else to add, just let me know:
REF:- Vacuum Tube GE 9-22 188-5
- 2N2905A BJT - PNP, -60 V, -600 mA, 600 mW, TO-39
- TTL 74F00 IC - 5V, quad 2-input NAND gate; series F (=fast) introduced in 1978
- 64Gb NAND flash memory card