Showing posts with label ESSDERC. Show all posts
Showing posts with label ESSDERC. Show all posts

Dec 18, 2023

[C4P] 50th ESSERC, Sept. 9-12. 2024, Bruges (BE)

CALL FOR PAPERS
https://www.esserc2024.org/papers

The aim of ESSERC (European Solid-State Electronics Conference) is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. It is a continuation of the past ESSDERC-ESSCIRC conferences. The level of integration for system-on-chip design is rapidly increasing. This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers and system designers is necessary. 
ESSERC is governed by a Steering Committee and consists of Plenary Keynote Presentations, invited papers and session on technology, circuits and joint papers bridging both device and circuit communities, respectively. 

PAPERS SUBMISSION DEADLINE: APRIL 5, 2024

Papers submitted for review must clearly state:
  • The purpose of the work
  • How and to what extent it advances the state-of-the art
  • Specific results and their impact
Only work that has not been previously published or submitted elsewhere will be considered. Submission of a paper for review and subsequent acceptance is considered as a commitment that the work will not be publicly available prior to the conference. Measurement results or calibration against measured data is required to support the claims of the submitted paper.

After selection of papers, the authors will be informed about the decision of the Technical Program Committee by e-mail by 24 May 2024.

At the same time, the complete program will be published on the conference website. An oral presentation will be given at the Conference for each accepted paper. No-shows will result in the exclusion of the papers from any conference related publication. The submitted final PDF files should be IEEE Xplore compliant.

For each paper independently, at least one (co-)author is required to register for the Conference (one registration one paper policy). Registration fees and deadlines will be soon available

CONFERENCE TRACKS (although not limited, papers are solicited for the following main topics):
  1. Advanced Technology, Process and Materials
  2. Analog, Power and RF Devices
  3. Compact Modeling and Process/Device Simulation
    TCAD and advanced simulation techniques and studies, compact/ SPICE modeling of electronic, optical, organic, emerging, and hybrid devices and their IC implementation and interconnection. Verilog-A models of semiconductor devices (including bio/ med sensors, MEMS, microwave, RF, high voltage and power, emerging technologies, and novel devices), parameter extraction, reliability and variability, performance evaluation and open-source benchmarking/implementation methodologies. Modeling of interactions between process, device and circuit design, design/technology co-optimization, foundry/fabless interface strategies. Numerical, analytical, statistical modeling and simulation of electronic, optical and hybrid devices, interconnect, isolation, and 2D/3D integration. Simulations of material properties and fabrication processes. Advanced physical phenomena (quantum mechanical and non-stationary transport phenomena, ballistic transport). Mechanical and/or electro-thermal modeling and simulation. Simulations of reliability aspects of materials and devices.
  4. Analog Circuits
  5. Data Converters
  6. RF & mm-Wave Circuits
  7. Frequency Generation Circuits
  8. Digital Circuits & Systems
  9. Power Management
  10. Wireless Systems
  11. Wireline and Optical Circuits and Systems
  12. Emerging Computing Devices and Circuits
  13. Architectures and Circuits for AI and ML
  14. Devices & Circuits for Sensors, Imagers and Displays
WHY BRUGES?
Bruges is a place that lives and breathes history. Visiting this historic city means travelling back in time to the Middle Ages. It is both magical and authentic. Brugge in medieval times was known as a commercial metropolis in the heart of Europe. 
Bruges is one of Europe’s best-preserved cities, evidenced by the fact that its historic city center has been designated an UNESCO World Heritage Site. The iconic spires of its cathedral and bell tower, its cobbled streets, winding canals and whitewashed façades are almost painfully picturesque.
In the 15th century, Brugge was the cradle of the Flemish Primitives and a center of patronage and painting development for artists such as Jan van Eyck and Hans Memling. Many of their works were exported and influenced painting styles all over Europe. Exceptionally important collections have remained in the city until today. Travelers from all over the world are coming to Belgium to visit Bruges.

Feb 3, 2022

[ESSDERC/ESSCIRC 2022] Call for Papers

Paper submission is open!
Submission deadline: Apr 12, 2022 23:59 (GMT -0700)
Decision notification: May 31, 2022 23:59 (GMT -0700)

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. The level of integration for system-on- chip design is rapidly increasing. This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers and system designers is necessary. While keeping separate Technical Program Committees, ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both communities. Attendees registered for either conference are encouraged to attend any of the scheduled parallel sessions, regardless to which conference they belong.

PAPER SUBMISSION
Manuscript guidelines as well as instructions on how to submit electronically will be available on this website. Papers must not exceed four A4 pages with all illustrations and references included.
THE PAPERS SUBMISSION DEADLINE: APRIL 12, 2022

Papers submitted for review must clearly state:
•The purpose of the work
•How and to what extent it advances the state-of-the art
•Specific results and their impact

Only work that has not been previously published or submitted elsewhere will be considered. Submission of a paper for review and subsequent acceptance is considered as a commitment that the work will not be publicly available prior to the conference. After selection of papers, the authors will be informed about the decision of the Technical Program Committee by e-mail by 31 May 2022.

At the same time, the complete program will be published on the conference website. A binary feedback (accepted/rejected) with no comments will be provided to the authors. An oral presentation will be given at the Conference for each accepted paper. No-shows will result in the exclusion of the papers from any conference related publication. The submitted final PDF files should be IEEE Xplore compliant.

Nov 24, 2021

ESSCIRC/ESSDERC 2021 The Best Paper Awards

The #ESSCIRC #ESSDERC TPC is proud to announce The Best Paper Awards from ESSCIRC/ESSDERC 2021 in Grenoble, selected by our Technical Program Committee members:
  • BEST JOINT PAPER 2021: “Low Power Indirect Time-of-Flight Pixel Achieving 88.5% Demodulation Contrast at 200MHz for 0.54MPix Depth Camera” by Cedric Tubert et al., STM (F)
  • BEST STUDENT JOINT PAPER 2021: “Cryogenic Characterization and Modeling of 14 nm Bulk FinFET Technology”, by @Asma Chabane, IBM Research GmbH
  • BEST ESSDERC PAPER 2021: “Complementary Two-Dimensional (2-D) MoS_2 FET Technology”, by @Cristine Jin Estrada et al., The Hong Kong UST
  • BEST ESSDERC STUDENT PAPER 2021:“VERILOR: a Verilog-a Model of Lorentzian Spectra for Simulating Trap-Related Noise in CMOS Circuits”, by @Angeliki Tataridou, IMEP-LaHC, Université Grenoble Alpes, University Savoie Mont Blanc, CNRS, Grenoble INP
  • BEST ESSCIRC PAPER 2021: “A Resolution-Adaptive 8mm2 9.98Gb/S 39.7pJ/B 32-Antenna All-Digital Spatial Equalizer for mmWave Massive MU-MIMO in 65nm CMOS”, by @Oscar Castaneda et al., ETH Zürich and Cornell Univ.
  • BEST ESSCIRC STUDENT PAPER 2021:”A −109.1 dB/−98 dB THD/THD+N Chopper Class-D Amplifier with >83.7 dB PSRR Over the Entire Audio Band”, by @Huajun Zhang et al., TU Delft
Warm congratulations to all the authors, and see you in Milano, September 19-22, 2022 at #ESSCIRC-#ESSDERC Conference for the Award Ceremony!

Sylvain CLERC Francois Andrieu Louis Hutin 
on the behalf off#ESSCIRC #ESSDERC TPC








Nov 17, 2020

[paper] Editorial Special Section on ESSDERC

IEEE TED, Vol. 67, No. 11, November 2020

Mid-September 2020, we were supposed to celebrate in Grenoble the 50th anniversary of the European SolidState Device Research Conference and European Solid-State Circuits Conference (ESSDERC-ESSCIRC), which is the most important European conference dedicated to solid-state devices and circuits. However, in April 2020, more than one-third of the global population was under severe lock-down as a result of the protective public health measures imposed by the different governments, states, or provinces. Because of the COVID-19 pandemic, the ESSDERC-ESSCIRC organizing and steering committees, together with the sponsoring SSCS and EDS IEEE societies, decided to reschedule the in-person conference to September 6–9, 2021, in Grenoble, to add new virtual “Educational Events” held on September 14 and 15, 2020 (presentations available till October 16, 2020, at https://www.esscirc-essderc2020.org/) as well as to invite the ESSDERC-ESSCIRC research community to submit publications to the IEEE TRANSACTIONS ON ELECTRON DEVICES (TED) and to the IEEE SOLID-STATE CIRCUITS LETTERS (SSC-L), respectively, in a brief format. All of these initiatives met great success. Especially, more than 47 TED submissions were received and reviewed, and 32 papers were accepted and have been included in this dedicated section of the November TED issue.

We would like to thank all the authors for taking this opportunity to keep the ESSDERC-ESSCIRC momentum, all the IEEE reviewers for their reactivity, and all the ESSDERC-ESSCIRC sponsors for their trust in this difficult time. Let us think with a positive mind, and acknowledge that this experience opens a new and fruitful collaboration between ESSDERC and TED.

We hope you will enjoy reading these high-quality papers. Stay safe

FRANCOIS ANDRIEU, TPC Chair
CEA-Leti
Université Grenoble Alpes
38054 Grenoble, France

GIOVANNI GHIONE, Editor-in-Chief
Dipartimento di Elettronica e Telecomunicazioni
Politecnico di Torino
10129 Torino, Italy
Editorial Special Section on ESSDERC
 IEEE TED, Vol. 67, No. 11, November 2020
  1. Generalized Constant Current Method for Determining MOSFET Threshold Voltage M. Bucher, N. Makris, and L. Chevas pp.4559
  2. Performance and Low-Frequency Noise of 22-nm FDSOI Down to 4.2 K for Cryogenic Applications (Invited Paper) B. Cardoso Paz, M. Cassé, C. Theodorou, G. Ghibaudo, T. Kammler, L. Pirro, M. Vinet, S. de Franceschi, T. Meunier, and F. Gaillard pp.4563
  3. A Method for Series-Resistance-Immune Extraction of Low-Frequency Noise Parameters in Nanoscale MOSFETs A. Tataridou, G. Ghibaudo, and C. Theodorou pp.4568
  4. Analytical Model for Interface Traps-Dependent Back Bias Capability and Variability in Ultrathin Body and Box FDSOI MOSFETs W. Chen, L. Cai, X. Liu, and G. Du pp.4573
  5. Polarization Independent Band Gaps in CMOS Back-End-of-Line for Monolithic High-Q MEMS Resonator Confinement R. Hudeczek and P. Baumgartner pp.4578
  6. Out-of-Equilibrium Body Potential Measurement on Silicon-on-Insulator With Deposited Metal Contacts M. Alepidis, A. Bouchard, C. Delacour, M. Bawedin, and I. Ionica pp.4582
  7. Evaluation of High-Temperature High-Frequency GaN-Based LC-Oscillator Components A. Ottaviani, P. Palacios, T. Zweipfennig, M. Alomari, C. Beckmann, D. Bierbüsse, J. Wieben, J. Ehrler, H. Kalisch, R. Negra, A. Vescan, and J. N. Burghartz pp.4587
  8. Analysis of Gate-Metal Resistance in CMOS-Compatible RF GaN HEMTs R. Y. ElKashlan, R. Rodriguez, S. Yadav, A. Khaled, U. Peralagu, A. Alian, N. Waldron, M. Zhao, P. Wambacq, B. Parvais, and N. Collaert pp.4592
  9. Characterization and TCAD Modeling of Mixed-Mode Stress Induced by Impact Ionization in Scaled SiGe HBTs N. Zagni, F. M. Puglisi, G. Verzellesi, and P. Pavan pp.4597
  10. Hot-Electron Effects in AlGaN/GaN HEMTs Under Semi-ON DC Stress A. Minetto, B. Deutschmann, N. Modolo, A. Nardo, M. Meneghini, E. Zanoni, L. Sayadi, G. Prechtl, S. Sicre, and O. Häberlen pp.4602
  11. Vertically Replaceable Memory Block Architecture for Stacked DRAM Systems by Wafer-on-Wafer (WOW) Technology S. Sugatani, N. Chujo, K. Sakui, H. Ryoson, T. Nakamura, and T. Ohba pp.4606
  12. Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays T. Zanotti, C. Zambelli, F. M. Puglisi, V. Milo, E. Pérez, M. K. Mahadevaiah, O. G. Ossorio, C. Wenger, P. Pavan, P. Olivo, and D. Ielmini pp.4611
  13. IGZO-Based Compute Cell for Analog In-Memory Computing—DTCO Analysis to Enable Ultralow-Power AI at Edge D. Saito, J. Doevenspeck, S. Cosemans, H. Oh, M. Perumkunnil, I. A. Papistas, A. Belmonte, N. Rassoul, R. Delhougne, G. Kar, P. Debacker, A. Mallik, D. Verkest, and M. H. Na pp.4616
  14. Array-Level Programming of 3-Bit per Cell Resistive Memory and Its Application for Deep Neural Network Inference Y. Luo, X. Han, Z. Ye, H. Barnaby, J.-s. Seo, and S. Yu pp.4621
  15. Ultrahigh-Density 3-D Vertical RRAM With Stacked Junctionless Nanowires for In-Memory-Computing Applications M. Ezzadeen, D. Bosch, B. Giraud, S. Barraud, J.-P. Noël, D. Lattard, J. Lacord, J. M. Portal, and F. Andrieu pp.4626
  16. Thermal Stress-Aware CMOS–SRAM Partitioning in Sequential 3-D Technology S. M. Salahuddin, E. Dentoni Litta, A. Gupta, R. Ritzenthaler, M. Schaekers, J.-L. Everaert, H. Yu, A. Vandooren, J. Ryckaert, M.-H. Na, and A. Spessot pp.4631
  17. Cryogenic Operation of Thin-Film FDSOI nMOS Transistors: The Effect of Back Bias on Drain Current and Transconductance M. Cassé, B. Cardoso Paz, G. Ghibaudo, T. Poiroux, S. Barraud, M. Vinet, S. de Franceschi, T. Meunier, and F. Gaillard pp.4636
  18. Enhanced Ultraviolet Avalanche Photodiode With 640-nm-Thin Silicon Body Based on SOI Technology I. Sabri Alirezaei, N. Andre, and D. Flandre pp.4641
  19. TCAD Study of VLD Termination in Large-Area Power Devices Featuring a DLC Passivation L. Balestra, S. Reggiani, A. Gnudi, E. Gnani, J. Dobrzynska, and J. Vobecký pp.4645
  20. Analysis of MIS-HEMT Device Edge Behavior for GaN Technology Using New Differential Method R. Kom Kammeugne, C. Leroux, J. Cluzel, L. Vauche, C. Le Royer, R. Gwoziecki, J. Biscarrat, F. Gaillard, M. Charles, E. Bano, and G. Ghibaudo pp.4649
  21. Influence of Substrate Resistivity on Porous Silicon Small-Signal RF Properties G. Godet, E. Augendre, J. Lugo-Alvarez, H. Jacquinot, F. X. Gaillard, T. Lorne, E. Rolland, T. Taris, and F. Servant pp.4654
  22. Free Carrier Mobility, Series Resistance, and Threshold Voltage Extraction in Junction FETs N. Makris, M. Bucher, L. Chevas, F. Jazaeri, and J.-M. Sallese pp.4658
  23. Local Variability Evaluation on Effective Channel Length Extracted With Shift-and-Ratio Method J. P. Martinez Brito and S. Bampi pp.4662
  24. Charge-Based Model for the Drain-Current Variability in Organic Thin-Film Transistors Due to Carrier-Number and Correlated-Mobility Fluctuation A. Nikolaou, G. Darbandy, J. Leise, J. Pruefer, J. W. Borchert, M. Geiger, H. Klauk, B. Iniguez, and A. Kloes pp.4667
  25. Macromodel for AC and Transient Simulations of Organic Thin-Film Transistor Circuits Including Nonquasistatic Effects J. Leise, J. Pruefer, A. Nikolaou, G. Darbandy, H. Klauk, B. Iniguez, and A. Kloes pp.4672
  26. Compact Modeling and Behavioral Simulation of an Optomechanical Sensor in Verilog-A H. Elmi Dawale, L. Sibeud, S. Regord, G. Jourdan, S. Hentz, and F. Badets pp.4677
  27. TCAD Simulation Framework of Gas Desorption in CNT FET NO2 Sensors S. Carapezzi, S. Reggiani, E. Gnani, and A. Gnudi pp.4682
  28. Conductance in a Nanoribbon of Topologically Insulating MoS2 in the 1T Phase V. Sverdlov, A.-M. B. El-Sayed, H. Kosina, and S. Selberherr pp.4687
  29. Vt Extraction Methodologies Influence Process Induced Vt Variability: Does This Fact Still Hold for Advanced Technology Nodes? M. S. Bhoir, T. Chiarella, J. Mitard, N. Horiguchi, and N. R. Mohapatra pp.4691
  30. Multidomain Negative Capacitance Effect in P(VDF-TrFE) Ferroelectric Capacitor and Passive Voltage Amplification K. J. Singh, A. Bulusu, and S. Dasgupta pp.4696
  31. Monte Carlo Comparison of n-Type and p-Type Nanosheets With FinFETs: Effect of the Number of Sheets F. M. Bufler, D. Jang, G. Hellings, G. Eneman, P. Matagne, A. Spessot, and M. H. Na pp.4701
  32. Impact of Width Scaling and Parasitic Series Resistance on the Performance of Silicene Nanoribbon MOSFETs M. Poljak pp.4705

Jun 9, 2020

Virtual Education Events at ESSDERC/ESSCIRC 2020


Given this uncertain situation, the organizing committee of ESSDERC/ESSCIRC 2020 in Grenoble and its Steering Committee, have decided to propose a new format for coming conference, which will include a NEW and Virtual Education Event series being developed for September 14th 2020 consisting of 13 educational sessions (workshops and tutorial) comprising invited presentations by leading academic and industrial experts and technologists. All related technical program details are also available online: https://www.esscirc-essderc2020.org/educationals

1. TUTORIAL | Quantum Computing: Myth or Reality?
Chairs: M. Vinet (CEA) and Farhana Sheikh (Intel)
Full content duration ~6h
2. WORKSHOP | Emerging Solutions for Imaging Devices, Circuits and Systems
Chairs: Matteo Perenzoni (FBK) and Albert Theuwissen (Harvest Imaging)
Full content duration ~6h
3. WORKSHOP | Non-Volatile Memories: Opportunities and Challenges from Devices to Systems
Chairs: Gabriel Molas (CEA) and Mahmut Sinangil (TSMC)
Full content duration ~6h
4. WORKSHOP | New 5G integration solutions, and related technologies (from materials to system)
Chairs: Nadine Collaert (imec) and Stefan G. Andersson (Ericsson)
Full content duration ~6h
5. WORKSHOP | Advances in device technologies for automotive industry (power devices, SiC, GaN)
Chairs: Ionut Radu (Soitec) and Stefaan Decoutere (IMEC)
Full content duration ~6h
6. WORKSHOP | Embedded monitoring and compensation design for energy or safety constrained applications
Chairs: Sylvain Clerc (ST) and Keith Bowman (Qualcomm)
Full content duration ~4h
7. WORKSHOP | Edge AI and In-Memory-Computing for energy efficient AIoT solutions​
Chairs:  Andreas Burg (EPFL) and Marian Verhelst (KUL)
Full content duration ~6h
8. WORKSHOP | Ab-initio simulations supporting new materials & process developments
Chairs: Denis Rideau (ST) and Philippe Blaise (Silvaco)
Full content duration ~3h
9. WORKSHOP | RISC-V cooking session
Chairs: Bora Nikolic (BWRC)
Full content duration ~3h
10. DISSEMINATION WORKSHOP |  Toward sustainable IOT from rare materials to big data
Chairs:  Thierry Baron (CEA, LTM/UGA) and Audrey Dieudonné (UGA)
Full content duration ~3h
11. DISSEMINATION WORKSHOP | High Density 3D CMOS Mixed-Signal Opportunities
Chair: Philipp Häfliger (UiO)
Full content duration ~3h
12. MOS-AK WORKSHOP | Compact/SPICE Modeling and its Verilog-A Standardization
Chair: Wladek Grabinski (MOS-AK) and Daniel Tomaszewski (ITE Warsaw)
Full content duration ~6h
13. IPCEI on Microelectronics: Innovative Technologies for Shaping the Future
Chairs: Dominique Thomas (ST), Klaus Pressel (Infineon), Rainer Pforr (Zeiss)
Full content duration ~6h

Apr 1, 2020

[C4P] ESSDERC TRACK3 Compact Modeling


European ESSDERC/ESSCIRC conference will be organized in Grenoble (F) on Sept.14-18, 2020 with its integral TRACK3: Compact Modeling and Process/Device Simulation which is open for submissions, now. You and all your R&D partners are welcome to submit a modeling paper. The paper submission deadline is April 17, 2020

TRACK3: Compact modeling and process/device simulation (including TCAD and advanced simulation techniques and studies)  focuses on following domains among other R&D topics:
  • Compact/SPICE modeling of electronic, optical, organic, and hybrid devices and their IC implementation and interconnection. 
  • Verilog-A models of the semiconductor devices (including Bio/Med sensors, MEMS, Microwave, RF, HV and Power, emerging technologies and novel devices)
  • Compact/SPICE parameter extraction
  • Performance evaluation and open source (FOSS) benchmarking/implementation methodologies
  • Modeling of interactions between process, device and circuit design, 
  • Foundry/Fabless interface strategies
  • Numerical TCAD, analytical, statistical modeling and simulation of electronic, optical and hybrid devices, interconnect, isolation and 2D/3D integration
  • Aspects of materials, fabrication processes and devices e.g. advanced physical phenomena (quantum mechanical and non-stationary transport phenomena, ballistic transport, ...)
  • Optical, mechanical or electro-thermal modeling and simulation
  • DfM, ageing, reliability of materials and devices
Please share our TRACK3 C4P with all your academic and industrial R&D partners active in the compact/SPICE modeling, Verilog-A standardization and TCAD/EDA simulations. Of course, your and your research team proactive contribution to our TRACK3 is more than welcome. I do hope that despite of a last minute notice, with your help, we will be able to draw even more attention to the ESSDERC/ESSCIRC Conference and, in particular, our modeling TRACK3



Mar 12, 2020

ESSCIRC ESSDERC 2020 | TPC Meeting goes VIRTUAL


GRENOBLE (FRANCE) - September 14-18, 2020

Dear TPC members,​
The safety and health of all ESSCIRC-ESSDERC TPC and Steering Committee members, and generally of IEEE SSCS and EDS members, volunteers, and attendees of SSCS and EDS events are our first priority. Given the currently sanitary situation related to corona-virus, and after consulting with our Steering Committee and SSCS and EDS direction, the ESSCIRC-ESSDERC 2020 Conference Organizing Committee has decided to organize a virtual paper selection meeting. We want to ensure a high scientific quality of the paper selection process, and we want to make sure each TPC member can provide high quality feedback in the same manner.

Regarding the different meeting:

  • The virtual participation of ALL TPC members is mandatory
  • We are currently working on the organization modalities, and we will inform you soon about the practical organization: phone bridges and screen sharing software will be put in place for each track in order to properly be able to discuss and select the best papers
  • We will try to accommodate a time schedule fitting to most of WW time zones represented in our TPC
  • The final dates of this virtual meeting will be very close to the initially scheduled one, i.e. May 18th 2020 for the TPC meeting, and May 19th for the SC meetings

The paper submission deadline stays the same, April 17th, and we strongly encourage you and your research teams to submit papers. As well, please do advertise among your personal networks the paper submission to our conference.
On a more positive note, ESSCIRC-ESSDERC 2020 paper selection meeting will be the first full virtual SSCS/EDS of such type of meeting. With this new experience, we will learn new ways to better serve our community and also reduce our carbon footprint.
Thank you very much for your understanding, and we count on the support of each and every TPC and SC member to make of ESSCIRC-ESSDERC 2020 a successful conference even in times of crisis!

Kind regards,

Andreia Cathelin, ESSCIRC TPC chair
Sylvain Clerc, ESSCIRC TPC co-chairFrancois
Andrieu, ESSDERC TPC chair
Maud Vinet, ESSDERC TPC co-chair
Thomas Ernst, General Chair
Dominique Thomas, General co-chair











x

Dec 2, 2019

[C4P] 50th ESSDERC / 46th ESSCIRC

Grenoble (F) Sept.14-18 2020
Call for Papers

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. The level of integration for system-on-chip design is rapidly increasing. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers and system designers is necessary. While keeping separate Technical Program Committees, ESSDERC and ESSCIRC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both communities. Attendees registered for either conference are encouraged to attend any of the scheduled parallel sessions, regardless to which conference they belong.

TPC Tracks:

  • Advanced Technology, Process and Materials
  • Analog, Power and RF Devices
  • Compact modeling and process/device simulation
  • Joint TRACK: Memory devices and circuits towards non Von Neumann
  • Joint TRACK: Emerging Computing Devices and Circuits
  • Joint TRACK: Devices and circuits for Sensors, Optoelectronics and Display
  • Analog Circuits
  • Data Converters Circuits
  • RF & mmW Circuits
  • Frequency Generation Circuits
  • Wireless & Wireline Circuits & Systems
  • Digital Circuits & Systems
  • Power Management Circuits

Apr 3, 2018

(NEW DEADLINE: 10 APRIL) ESSDERC Call for Papers

Call for Papers 
(NEW DEADLINE: 10 APRIL

PAPER SUBMISSION: Manuscript guidelines as well as instructions on how to submit electronically ARE AVAILABLE HERE. Papers must not exceed four A4 pages with all illustrations and references included. All submissions must be received by (NEW DEADLINE): 10 APRIL

Papers submitted for review must clearly state:

  • The purpose of the work
  • How and to what extent it advances the state-of-the-art
  • Specific results and their impact

Only work that has not been previously published or submitted elsewhere will be considered. Submission of a paper for review and subsequent acceptance is considered as a commitment that the work will not be publicly available prior to the conference [read more...]

Dec 19, 2016

[Call for Papers] ESSCIRC–ESSDERC 2017



September 11-14, 2017
LEUVEN - Belgium
www.esscirc-essderc2017.org

ESSCIRC–ESSDERC annual Conference is the most important European forum for the presentation and discussion of recent advances in solid-state devices and circuits: MAKE SURE TO BE PART OF IT!


LOCAL SCIENTIFIC SECRETARIAT
​Cor Claeys (imec, BE) | General Chair
Chantal Deboes (imec, BE) | ESSDERC Chair
Danielle Vermetten (KU Leuven, BE) | ESSCIRC Chair

ORGANIZERS   

TECHNICAL CO-SPONSORSHIP
ESSDERC FINANCIAL SPONSOR 
ESSCIRC FINANCIAL SPONSOR 
DIAMOND SPONSOR  

ORGANIZING SECRETARIAT: Sistema Congressi s.r.l. 










Feb 16, 2015

ESSCIRC/ESSDERC 2015 website is now active

 ESSCIRC/ESSDERC 2015 website is now active: www.esscirc-essderc2015.org

 The deadline for paper submission is 2 April, 2015.
 Looking forward to seeing you in Graz!

Prof. Wolfgang Pribyl: General Chair ESSCIRC/ESSDERC 2015
Franz Dielacher, Gernot Hueber: ESSCIRC TPC Chairs
Martin Schrems, Tibor Grasser: ESSDERC TPC Chairs

Jun 11, 2014

ESSDERC/ESSCIRC 2014 - Full conference program is now available

The technical programtutorial program, and workshop program of ESSDERC/ESSCIRC 2014
are now available at  ESSDERC/ESSCIRC 2014  website: http://www.esscirc-essderc2014.org 

Please remember to register to the conference and book a hotel room at before June 20, after 
which we cannot guarantee that you will find a hotel room at our rebated prices.
The event is technically co-sponsored by the
    IEEE Electron Device Society,
    IEEE Solid-State Circuit Society
    IEEE Circuits and Systems Society


We hope to see you in Venice

Best Regards
  Gaudenzio Meneghesso
ESSDERC/ESSCIRC 2014  General Chair

Roberto Bez and Paolo Pavan
ESSDERC 2014 TPC Chairs

Pietro Andreani and Andrea Bevilacqua 
ESSCIRC
 
2014 TPC Chairs


JOINT PLENARY TALKS 
Scott DeBoer
, Micron, ID, USA, A Semiconductor Memory Manufacturing and Development Perspective
Thomas H. Lee
, Stanford University, CA, USA Terahertz Electronics: The Last Frontier 
Fabio Marchiò
, STMicroelectronics, Italy, Automotive Electronics: Application & Technology Megatrends
Walter Snoeys
, CERN, Switzerland, How Chips Helped Discover the Higgs Boson at CERN
An Steegen
, IMEC, Belgium, Logic Scaling Beyond 10nm, a Power-Performance-Area-Cost Trade-off 
Sehat Sutardja
, Marvell Semiconductor, CA, USA Tremendous Benefits of Moore’s Law Have Yet to Come
ESSCIRC PLENARY TALKS
Hooman Darabi
, Broadcom Corporation, CA, USA Blocker Tolerant Software Defined Receivers
Un-Ku Moon, Oregon State University, OR, USA Emerging ADCs
Kathleen Philips
, IMEC-Holst Centre, The Netherlands Ultra-Low Power Short Range Radios
ESSDERC PLENARY TALKS
Umesh Mishra
, UCSB and TRanphorm, CA, USA,  GaN-based solutions from KHz to THz 
Eric Pop, Stanford University, CA, USA, Energy Efficiency and Conversion in 1D and 2D Electronics
Takao Someya
, University of Tokyo, Japan Bionic Skins Using Flexible Organic Devices

ESSCIRC TUTORIALS
Power Management for SoCs (Full Day), Organizer: Christoph Sandner, Infineon, Austria
High Performance Amplifiers 
(Half Day), Organizer: Angelo Nagari, STMicroelectronics, France
Phase Noise: from Fundamentals to Circuit Aspects (Half Day) Organizer: Christian Enz, EPFL, Switzerland
ESSDERC TUTORIALS
CMOS Technology at the nm Scale Era 
(Full Day) Organizer: Maud Vinet, CEA LETI, France
RRAM: from Technology to Applications (Half Day) Organizer: Bogdan Govoreanu, IMEC, Belgium 
3D: from Technology to Applications 
(Half Day) Organizer: Pascal Vivet, CEA LETI, France

ESSDERC/ESSCIRC Workshops
Beyond-CMOS for advanced More Moore and More than Moore applications
 
Organizers: Francis Balestra and Enrico Sangiorgi, Sinano Institute - Grenoble INP/CNRS, France
MOS-AK: Over Two Decades of Enabling Compact Modeling R&D Exchange   
Organizer: Wladek Grabinski, MOS-AK Group (EU),
Status of the GaN and SiC based device development
   
Organizer: Enrico Zanoni, University of Padova, DEI, Italy
THz-Workshop: Millimeter- and Sub-Millimeter-Wave circuit design and characterization
   
Organizer: Thomas Zimmer, University Bordeaux, France
Marie Curie ATWC
   
Organizer: Rinaldo Castello, University of Pavia and Marvell, Italy

Apr 3, 2014

ESSDERC/ESSCIRC 2014 - Paper submission deadline extension

the Organizing Committee decided to extend the paper submission deadline of the 44th ESSDERC and 40th ESSCIRC to:
April 16th, 2014 23:59 (GMT - 07:00 am)

This is a hard deadline and no further extensions will be granted. After the deadline is elapsed, further paper submissions will not be accepted. The notification of paper acceptance, May 27, 2014, has not changed. Detailed information about the conferences is provided at the ESSCIRC/ESSDERC 2014 website.

[read more...]

Jul 24, 2012

[mos-ak] Final Program: 10th MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Bordeaux, Sept. 21, 2012

Together with the Organizing Committee, Extended MOS-AK/GSA TPC Committee, and the IEEE EDS French Branch, the technical program sponsor, as well as with the industrial sponsors Agilent Technologies, LFoundry, CSEM, STM, AMS we have pleasure to invite to the 10th MOS-AK/GSA Compact Modeling Workshop at the ESSDERC/ESSCIRC Conference in Bordeaux, Sept. 21, 2012.  

The final workshop program is available on-line: <http://mos-ak.org/bordeaux/

To register please visit official ESSDERC/ESSCIRC registration website.

- with regards - WG (for the MOS-AK/GSA Committee
––––––––––––––––––––––––––––––––––---------------- 
MOS-AK/GSA Bordeaux (F) Sept.21, 2012 
MOS-AK/GSA San Francisco, CA Q4 2012 
––––––––––––––––––––––––––––––––––----------------