Showing posts with label EDS. Show all posts
Showing posts with label EDS. Show all posts

Mar 4, 2024

[EDTM] Inauguration Session

8th IEEE EDTM
March 3-6, 2024
Strengthening Globalization in Semiconductors

The 8th Electron Devices Technology and Manufacturing Conference (IEEE EDTM 2024) will be held for the first time in India at Bangalore; the Silicon Valley of India and the hub of semiconductor companies. IEEE EDTM 2024 will be a full four-day conference to be held during March 3-6, 2024. IEEE EDTM 2024 aims to be a premier global forum for researchers and engineers from around the world coming to share new discoveries and discuss any device/manufacturing-related topics, including but not limited to, materials, processes, devices, packaging, modeling, reliability, manufacturing and yield, tools, testing, and any emerging device technologies, as well as workforce training. 

Plenary Talk by Prof. Chenming Hu "Semiconductor – the Next 75 Years?"


Oct 17, 2023

[webinar] IEEE SCV-EDS: Investigating quantum speed limits with superconducting qubits

The Electron Devices Society Santa Clara Valley/San Francisco joint Chapter is hosting Prof. Meenakshi Singh. The title of the lecture is ‘Investigating quantum speed limits with superconducting qubits’

When: Friday, Oct. 20, 2023 – 9am to 10am (PDT)
Where: This is an online event and attendees can participate via Zoom.

Registration or Send an email to hiuyung.wong at ieee.org to get the zoom link indicating if you are IEEE member, IEEE EDS member, IEEE Student member

Abstract: The speed at which quantum entanglement between qubits with short range interactions can be generated is limited by the Lieb-Robinson bound. Introducing longer range interactions relaxes this bound and entanglement can be generated at a faster rate. The speed limit for this has been analytically found only for a two-qubit system under the assumption of negligible single qubit gate time. We seek to demonstrate this speed limit experimentally using two superconducting transmon qubits. Moreover, we aim to measure the increase in this speed limit induced by introducing additional qubits (coupled with the first two). Since the speed up grows with additional entangled qubits, it is expected to increase as the system size increases. This has important implications for large-scale quantum computing.

Speaker Bio: Dr. Singh is an experimental physicist with research focused on quantum thermal effects and quantum computing. She graduated from the Indian Institute of Technology with an M. S. in Physics in 2006 and received a Ph. D. in Physics from the Pennsylvania State University in 2012. Her Ph. D. thesis was focused on quantum transport in nanowires. She went on to work at Sandia National Laboratories on Quantum Computing as a post-doctoral scholar. She is currently an Associate Professor in the Department of Physics at the Colorado School of Mines. At Mines, her research projects include measurements of spin-orbit coupling in novel materials and thermal effects in superconducting hybrids. She recently received the NSF CAREER award to pursue research in phonon interactions with spin qubits in silicon quantum dots.

May 8, 2023

[EDS MQ/DL] The Transistor Turns 75

The Transistor Turns 75
A Forward Look to Challenges and Opportunities


A series of IEEE EDS Distinguished Lecturer talks on topics in current transistor and electron device research, reflecting on the challenges ahead and the rewards inherrent in overcomming them.

  DATE AND TIME LOCATION HOSTS REGISTRATION
Date: 02 Jun 2023
Time: 08:30 AM to 05:30 PM

All times are (UTC+00:00) Edinburgh
Moller Institute
Cambridge, England UK
CB3 ODE

Click here for Map
UK and Ireland Section Chapter, ED15

Contact Host
Starts 19 April 2023 06:00 AM
Ends 30 May 2023 06:30 PM
All times are (UTC+00:00) Edinburgh

No Admission Charge

Register Now

EDS DL SPEAKERS
  • Benjamin Iniguez: Modeling 2D Semiconductor Devices
  • Lluis Marsal: Organic Photovoltaics: Opportunities and Challenges
  • Arokia Nathan: 
  • Fernando Guarin: 75th Anniversary of the Transistor Semiconductor Industry Perspective
  • Edmundo A. Gutierrez-D.: DC and RF reliability of advanced bulk and SOI CMOS technologies
  • Merlyne De Souza: Challenges to Edge computing: an era beyond silicon CMOS
  • Samar Saha: 
  • MK Radhakrishnan: Birth and Evolution of Transistor and Its Impact on Humanity
  • Xiaojun Guo: Transistor Technologies for Hybrid Integration at Micro- and Macro-scales
  • Hiroshi Iwai: Present status and future of the nanoelectronics technology

Feb 9, 2023

[Hisayo Momose] My Journey as a Researcher in the Semiconductor Field

graphical user interface, text, application 

Hisayo Mosmose's Story 

Read Hisayo Momose's article from the IEEE EDS January Newsletter, "My Journey as a Researcher in the Semiconductor Field."

Dr. Momose has more than 30 years of experience in research and development at Toshiba Corporation, Japan. She is a recipient of several awards and honors, and has authored or co-authored nearly 200 papers published in technical journals and conference proceedings [read more...]

#IEEE #EDS #ElectronDevices #WiEDS #womeinengineering #semiconductors
 

 

 

Jan 19, 2023

IEEE EDS MQ at NIT Silchar Silchar, Assam (IN)

IEEE EDS Mini-Colloquium 
on Micro/Nanoelectronics, Devices, Circuits and Systems, 
29-31 Jan 2023 (Hybrid Mode)

DATESLOCATIONHOSTREGISTER
Date: 29 Jan 2023
Time:10:00AM to 06:00PM
 (UTC+05:30) 
Add Event to Calendar
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National Institute of Technology Silchar
Dept of ECE,
NIT Silchar Silchar, Assam India 788010
Building: ECE/CSE Building


National Inst of Technology - Silchar,
ED15 Kolkata Section Chapter NANO42
Co-sponsored by Dr. Trupti R. Lenka


Starts
Dec.1, 2022
Ends
Jan.28,2023

No Admission Charge
Register NOW

Agenda with following contribution Distinguished Lecturers: 
  • Anil Kottantharayil (anilkg@ieee.org)
  • Gananath Dash (gndash@ieee.org)
  • Ajit Kumar Panda (akpanda62@hotmail.com)
  • Manoj Saxena (msaxena@ieee.org)
  • Brajesh Kumar Kaushik (bkkaushik23@gmail.com)
  • Samar Saha (samar@ieee.org)
  • Hiroshi Iwai (h.iwai@ieee.org)
  • Taiichi Otsuji (taiichi.otsuji.e8@tohoku.ac.jp)
  • Pei-Wen Li (pwli@nycu.edu.tw)
  • Zhou Xing (EXZHOU@ntu.edu.sg)
  • Albert Chin (albert_achin@hotmail.com)
  • Mansun Chan (mchan@ust.hk)
  • Chao-Sung LAI (cslai@mail.cgu.edu.tw)
  • Wladek Grabinski, MOS-AK, EU (wladek@grabinski.ch)

Jun 9, 2022

[Program] MINI-COLLOQUIUM ON CAD/EDA MODELING

MINI-COLLOQUIUM ON CAD/EDA MODELING
Sala de Graus, Campus ETSE/ETSEQ
Department of Electronic, Electrical and Automatic Control Engineering, 
University Rovira i Virgili Tarragona, Catalonia, Spain

Chairperson: 
Benjamin Iñiguez, EDS BoG Member and Chair of the ED Spain Chapter


Tuesday, June 28 2022

8:20-8:30 Overview, B. Iñiguez
8:30-9:30 “Characterization and TCAD modeling based design assessment of ultra-high voltage SiC devices,” Muhammad Nawaz (Hitachi Energy, Sweden)
9:30-10:30 “Nanoscale InGaAs FinFETs: Band-to-Band Tunneling and Ballistic Transport,” Jesús del Alamo (MIT, USA)

10:30-11:00 Coffee break

11:00-12:00 “Physics-Based Parameter Extraction for Thin Film Transistors,” Arokia Nathan (Darwin College, University of Cambridge, UK)
12:00-13:00; “Characterization and modeling of organic solar cells,” Lluís F. Marsal (University Rovira I Virgili, Tarragona, Spain)

13:00-15:00 Lunch

15:00-19:00 Meeting of the EDS SRC Region 8 Executive Committee

Wednesday, June 29 2022

11:00-12:00 “Trends and challenges in Nanoelectronics for the next decade,” Elena Gnani (University of Bologna, Italy)
12:00-13:00,“SPICE and Verilog-A Modelling Using FOSS TCAD/EDA Tools: Technology - Devices – Applications” (virtual), Wladek Grabinski (GMC, Switzerland)

13:00-14:20 Lunch

Joint Session 
  • MQ on CAD Modeling
  • Graduate Student Meeting on Electronic Engineering
14:20-14:30 Overview, B. Iñiguez and J. Ferré-Borrull
14:30-15:30 “Compact modeling of memristive devices for neuromorphic computing,” (virtual) Enrique Miranda (Autonomous University of Barcelona, Spain)
15:30-16:30 Physical Principles to Formulate Thin Film Transistor Models for Circuit Design (virtual), Samar Saha (Prospicient Devices, USA)

16:30-16:35 Closing remarks, B. Iñiguez

Mar 31, 2021

[webinar] "More Moore Roadmap" by IRDS and SINANO


IEEE EDS France, IRDS and the SINANO Institute will organize a Webinar 

"More Moore Roadmap"
by Mustafa Badaroglu 
IRDS-IFT More Moore Leader

The webinar will be held on 8th April 2021 at 16:00 Paris time. Interest participants please register via IEEE vTools by the following link: https://events.vtools.ieee.org/event/register/267103

Other Webinars of the IRDS Chapters will be announced in the EDS Newsletters

Jan 22, 2021

Joint Spring MOS-AK, SB-MOS and IEEE EDS MQ

Joint Spring MOS-AK Workshop and Symposium on Schottky Barrier MOS (SB-MOS) Devices
with IEEE EDS Mini-Colloquium on “Non-Conventional Devices and Technologies”
September 29 to October 1, 2020
THM Giessen (Germany)
—by Mike Schwarz— The Joint Spring MOS-AK Workshop and Symposium on Schottky Barrier MOS (SB-MOS) devices with IEEE EDS Mini-Colloquium on “Non-conventional Devices and Technologies” was held from September 29 to October 1, 2020. While it was initially planned for spring at THM—University of Applied Sciences in Giessen (Germany), it was shifted to the early autumn due to the COVID-19 pandemic. However, finally the local organizers of NanoP Competence Center for Nanotechnology and Photonics of THM decided to move it to Zoom and perform it virtually. It was sponsored by THM, the EDS Germany Chapter, the IEEE Young Professionals Germany Affinity Group, and the AdMOS company. The event was attended by 69 IEEE members and 115 non IEEE members (guests) from 25 countries during the three days [read more...]

Dec 15, 2020

[VIRTUAL] EDS MQ on Compact Modeling

VIRTUAL MINI-COLLOQUIUM ON COMPACT MODELING


IEEE EDS Compact Modeling Technical Committee
EDS Spain Chapter
Department of Electronic, Electrical and Automatic Control Engineering, 
University Rovira I Virgili, Tarragona (Spain)

December 17, 2020
EDS MQ Program (times in CET)
10:20-10:30
Benjamin Iñiguez, IEEE EDS MQ Chair
Department of Electronic, Electrical and Automatic Control Engineering, University Rovira I Virgili, Tarragona (Spain)
Opening session
10:30-11:15
Yogesh. S Chauhan
Department of Electrical Engineering,
Indian Institute of Technology Kanpur (India)
BSIM-BULK and BSIM-HV: Industry Standard SPICE Models for Analog, RFand High Voltage Applications
11:15-12:00
Manoj Saxena
Department of Electronics, University of Delhi  (India)
“Modeling and Simulation of Robust Ultrasensitive Tunnel Field Effect Transistor Design for Biosensing Applications”
12·00-12:45
Wladek Grabinski
GMC, Commugny (Switzerland)
FOSS TCAD/EDA Tools for Semiconductor Device Modeling
12:45-13:30
Arokia Nathan
Darwin College, University of Cambridge (UK)
“Physics-Based Parameter Extraction for TFTs”
13:30-15:00 Break
15:00-15:45
Marcelo Pavanello
Department of Electrical Engineering,
Centro Universitario FEI, Sao Bernardo do Campo (Brazil)
"Quantum Effects on the Mobility of SOI Nanowire MOSFETs Induced by the Active Substrate Bias"
15:45-16:30
Michael S. Shur
Department of Electrical, Systems and Computer Engineering,
Rensselaer Polytechnic Institute, Troy NY (USA)
THz Compact SPICE/ADS model
16:30-17:15
Edmundo Gutiérrez
Department of Electronics, INAOE, Puebla (Mexico)
"RF MOSFET degradation modeling up to 67 GHz”
End of EDS MQ

Dec 2, 2020

IEEE EDS Golden List of Reviewers

Golden List of Reviewers for 2020

Stat Data
CountryReviewers
USA559
China286
India159
Japan151
S.Korea121
Taiwan111
Italy102
Germany90
United Kingdom79
France64
Belgium63
Singapore35
Switzerland29
Austria28
Spain27
Hong Kong25
Russia22
Canada22
Netherlands19
Iran14
Brazil14
Turkey12
Australia12
Sweden10
Poland10
Greece10
Saudi Arabia8
Mexico8
Israel5
Ukraine4
Slovakia3
Portugal3
Malaysia3
Kazakhstan3
Egypt3
Algeria2
Bulgaria2
Denmark2
Finland2
Latvia2
Lithuania2
Qatar2
Romania2
Venezuela2
Bangladesh1
Belarus1
Croatia1
Czechia1
Ireland1
Kuwait1
Lebanon1
Macedonia1
Slovenia1
Tunisia1
UAE1

Nov 17, 2020

[paper] Editorial Special Section on ESSDERC

IEEE TED, Vol. 67, No. 11, November 2020

Mid-September 2020, we were supposed to celebrate in Grenoble the 50th anniversary of the European SolidState Device Research Conference and European Solid-State Circuits Conference (ESSDERC-ESSCIRC), which is the most important European conference dedicated to solid-state devices and circuits. However, in April 2020, more than one-third of the global population was under severe lock-down as a result of the protective public health measures imposed by the different governments, states, or provinces. Because of the COVID-19 pandemic, the ESSDERC-ESSCIRC organizing and steering committees, together with the sponsoring SSCS and EDS IEEE societies, decided to reschedule the in-person conference to September 6–9, 2021, in Grenoble, to add new virtual “Educational Events” held on September 14 and 15, 2020 (presentations available till October 16, 2020, at https://www.esscirc-essderc2020.org/) as well as to invite the ESSDERC-ESSCIRC research community to submit publications to the IEEE TRANSACTIONS ON ELECTRON DEVICES (TED) and to the IEEE SOLID-STATE CIRCUITS LETTERS (SSC-L), respectively, in a brief format. All of these initiatives met great success. Especially, more than 47 TED submissions were received and reviewed, and 32 papers were accepted and have been included in this dedicated section of the November TED issue.

We would like to thank all the authors for taking this opportunity to keep the ESSDERC-ESSCIRC momentum, all the IEEE reviewers for their reactivity, and all the ESSDERC-ESSCIRC sponsors for their trust in this difficult time. Let us think with a positive mind, and acknowledge that this experience opens a new and fruitful collaboration between ESSDERC and TED.

We hope you will enjoy reading these high-quality papers. Stay safe

FRANCOIS ANDRIEU, TPC Chair
CEA-Leti
Université Grenoble Alpes
38054 Grenoble, France

GIOVANNI GHIONE, Editor-in-Chief
Dipartimento di Elettronica e Telecomunicazioni
Politecnico di Torino
10129 Torino, Italy
Editorial Special Section on ESSDERC
 IEEE TED, Vol. 67, No. 11, November 2020
  1. Generalized Constant Current Method for Determining MOSFET Threshold Voltage M. Bucher, N. Makris, and L. Chevas pp.4559
  2. Performance and Low-Frequency Noise of 22-nm FDSOI Down to 4.2 K for Cryogenic Applications (Invited Paper) B. Cardoso Paz, M. Cassé, C. Theodorou, G. Ghibaudo, T. Kammler, L. Pirro, M. Vinet, S. de Franceschi, T. Meunier, and F. Gaillard pp.4563
  3. A Method for Series-Resistance-Immune Extraction of Low-Frequency Noise Parameters in Nanoscale MOSFETs A. Tataridou, G. Ghibaudo, and C. Theodorou pp.4568
  4. Analytical Model for Interface Traps-Dependent Back Bias Capability and Variability in Ultrathin Body and Box FDSOI MOSFETs W. Chen, L. Cai, X. Liu, and G. Du pp.4573
  5. Polarization Independent Band Gaps in CMOS Back-End-of-Line for Monolithic High-Q MEMS Resonator Confinement R. Hudeczek and P. Baumgartner pp.4578
  6. Out-of-Equilibrium Body Potential Measurement on Silicon-on-Insulator With Deposited Metal Contacts M. Alepidis, A. Bouchard, C. Delacour, M. Bawedin, and I. Ionica pp.4582
  7. Evaluation of High-Temperature High-Frequency GaN-Based LC-Oscillator Components A. Ottaviani, P. Palacios, T. Zweipfennig, M. Alomari, C. Beckmann, D. Bierbüsse, J. Wieben, J. Ehrler, H. Kalisch, R. Negra, A. Vescan, and J. N. Burghartz pp.4587
  8. Analysis of Gate-Metal Resistance in CMOS-Compatible RF GaN HEMTs R. Y. ElKashlan, R. Rodriguez, S. Yadav, A. Khaled, U. Peralagu, A. Alian, N. Waldron, M. Zhao, P. Wambacq, B. Parvais, and N. Collaert pp.4592
  9. Characterization and TCAD Modeling of Mixed-Mode Stress Induced by Impact Ionization in Scaled SiGe HBTs N. Zagni, F. M. Puglisi, G. Verzellesi, and P. Pavan pp.4597
  10. Hot-Electron Effects in AlGaN/GaN HEMTs Under Semi-ON DC Stress A. Minetto, B. Deutschmann, N. Modolo, A. Nardo, M. Meneghini, E. Zanoni, L. Sayadi, G. Prechtl, S. Sicre, and O. Häberlen pp.4602
  11. Vertically Replaceable Memory Block Architecture for Stacked DRAM Systems by Wafer-on-Wafer (WOW) Technology S. Sugatani, N. Chujo, K. Sakui, H. Ryoson, T. Nakamura, and T. Ohba pp.4606
  12. Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays T. Zanotti, C. Zambelli, F. M. Puglisi, V. Milo, E. Pérez, M. K. Mahadevaiah, O. G. Ossorio, C. Wenger, P. Pavan, P. Olivo, and D. Ielmini pp.4611
  13. IGZO-Based Compute Cell for Analog In-Memory Computing—DTCO Analysis to Enable Ultralow-Power AI at Edge D. Saito, J. Doevenspeck, S. Cosemans, H. Oh, M. Perumkunnil, I. A. Papistas, A. Belmonte, N. Rassoul, R. Delhougne, G. Kar, P. Debacker, A. Mallik, D. Verkest, and M. H. Na pp.4616
  14. Array-Level Programming of 3-Bit per Cell Resistive Memory and Its Application for Deep Neural Network Inference Y. Luo, X. Han, Z. Ye, H. Barnaby, J.-s. Seo, and S. Yu pp.4621
  15. Ultrahigh-Density 3-D Vertical RRAM With Stacked Junctionless Nanowires for In-Memory-Computing Applications M. Ezzadeen, D. Bosch, B. Giraud, S. Barraud, J.-P. Noël, D. Lattard, J. Lacord, J. M. Portal, and F. Andrieu pp.4626
  16. Thermal Stress-Aware CMOS–SRAM Partitioning in Sequential 3-D Technology S. M. Salahuddin, E. Dentoni Litta, A. Gupta, R. Ritzenthaler, M. Schaekers, J.-L. Everaert, H. Yu, A. Vandooren, J. Ryckaert, M.-H. Na, and A. Spessot pp.4631
  17. Cryogenic Operation of Thin-Film FDSOI nMOS Transistors: The Effect of Back Bias on Drain Current and Transconductance M. Cassé, B. Cardoso Paz, G. Ghibaudo, T. Poiroux, S. Barraud, M. Vinet, S. de Franceschi, T. Meunier, and F. Gaillard pp.4636
  18. Enhanced Ultraviolet Avalanche Photodiode With 640-nm-Thin Silicon Body Based on SOI Technology I. Sabri Alirezaei, N. Andre, and D. Flandre pp.4641
  19. TCAD Study of VLD Termination in Large-Area Power Devices Featuring a DLC Passivation L. Balestra, S. Reggiani, A. Gnudi, E. Gnani, J. Dobrzynska, and J. Vobecký pp.4645
  20. Analysis of MIS-HEMT Device Edge Behavior for GaN Technology Using New Differential Method R. Kom Kammeugne, C. Leroux, J. Cluzel, L. Vauche, C. Le Royer, R. Gwoziecki, J. Biscarrat, F. Gaillard, M. Charles, E. Bano, and G. Ghibaudo pp.4649
  21. Influence of Substrate Resistivity on Porous Silicon Small-Signal RF Properties G. Godet, E. Augendre, J. Lugo-Alvarez, H. Jacquinot, F. X. Gaillard, T. Lorne, E. Rolland, T. Taris, and F. Servant pp.4654
  22. Free Carrier Mobility, Series Resistance, and Threshold Voltage Extraction in Junction FETs N. Makris, M. Bucher, L. Chevas, F. Jazaeri, and J.-M. Sallese pp.4658
  23. Local Variability Evaluation on Effective Channel Length Extracted With Shift-and-Ratio Method J. P. Martinez Brito and S. Bampi pp.4662
  24. Charge-Based Model for the Drain-Current Variability in Organic Thin-Film Transistors Due to Carrier-Number and Correlated-Mobility Fluctuation A. Nikolaou, G. Darbandy, J. Leise, J. Pruefer, J. W. Borchert, M. Geiger, H. Klauk, B. Iniguez, and A. Kloes pp.4667
  25. Macromodel for AC and Transient Simulations of Organic Thin-Film Transistor Circuits Including Nonquasistatic Effects J. Leise, J. Pruefer, A. Nikolaou, G. Darbandy, H. Klauk, B. Iniguez, and A. Kloes pp.4672
  26. Compact Modeling and Behavioral Simulation of an Optomechanical Sensor in Verilog-A H. Elmi Dawale, L. Sibeud, S. Regord, G. Jourdan, S. Hentz, and F. Badets pp.4677
  27. TCAD Simulation Framework of Gas Desorption in CNT FET NO2 Sensors S. Carapezzi, S. Reggiani, E. Gnani, and A. Gnudi pp.4682
  28. Conductance in a Nanoribbon of Topologically Insulating MoS2 in the 1T Phase V. Sverdlov, A.-M. B. El-Sayed, H. Kosina, and S. Selberherr pp.4687
  29. Vt Extraction Methodologies Influence Process Induced Vt Variability: Does This Fact Still Hold for Advanced Technology Nodes? M. S. Bhoir, T. Chiarella, J. Mitard, N. Horiguchi, and N. R. Mohapatra pp.4691
  30. Multidomain Negative Capacitance Effect in P(VDF-TrFE) Ferroelectric Capacitor and Passive Voltage Amplification K. J. Singh, A. Bulusu, and S. Dasgupta pp.4696
  31. Monte Carlo Comparison of n-Type and p-Type Nanosheets With FinFETs: Effect of the Number of Sheets F. M. Bufler, D. Jang, G. Hellings, G. Eneman, P. Matagne, A. Spessot, and M. H. Na pp.4701
  32. Impact of Width Scaling and Parasitic Series Resistance on the Performance of Silicene Nanoribbon MOSFETs M. Poljak pp.4705

Nov 4, 2020

IEEE Germany EDS Chapter Elections

The IEEE Germany EDS Chapter has elected new ExCom members for the term 2020/2021. An exciting new leadership team has been built to establish EDS activities in Germany.

The new ExCom:
  • Chair: Mike Schwarz (TH Mittelhessen)
  • Vice Chair: Joachim Burghartz (Universität Stuttgart, IMS Chips)
  • Treasurer: Manfred Berroth (Universität Stuttgart)
  • Secretary: Sevda Abadpour (Karlsruhe Institute of Technology)
Further information is available online https://r8.ieee.org/germany-eds

Nov 3, 2020

Congratulations to Prof. Robert W. Dutton

The 2020 IEEE EDS Celebrated Member and Esteemed EDS Alumni


Dr. Dutton received his degrees from the University of California, Berkeley, and currently instructs electrical engineering at Stanford University. Current members of EDS take pride in the Celebrated Members' accomplishments, drawing from their achievements as inspiration to advance and achieve success in various fields. The award presentation will be held virtually during the 2020 IEDM in December [read more...]

ROBERT W. DUTTON
Robert W. Dutton received the B.S., M.S., and Ph.D. in Electrical Engineering degrees from the University of California, Berkeley, in 1966, 1967, and 1970, respectively. 
He is currently Robert and Barbara Kleist Professor of Electrical Engineering at Stanford University, and Associate Chair for Undergraduate Education. He has held summer staff positions at Fairchild, Bell Telephone Laboratories, Hewlett‐Packard, IBM Research, and Matsushita during 1967, 1973, 1975, 1977, and 1988 respectively. His research interests focus on integrated circuit process, device, and circuit technologies, especially the use of computer‐aided design (CAD) and parallel computational methods. He has published more than 200 journal articles and graduated more than four dozen doctorate students. 
Dr. Dutton was Editor of the IEEE Transactions on Computer Aided Design from 1984 to 1986, the winner of the 1987 IEEE J. J. Ebers Award, 1988 Guggenheim Fellowship to study in Japan, elected to the National Academy of Engineering in 1991, 1996 Jack A. Morton Award, 2000 C&C Prize Japan, University Researcher Award, Semiconductor Industry Association (2000), Phil Kaufman Award, Electronic Design Automation Consortium (2006), and 2014 Bass University Fellow in Undergraduate Education Program, Stanford University.

Jun 22, 2020

[virtual] IEEE EDS DL Mini-Colloquium at MIXDES Wroclaw


EDS Distinguished Lecturer Mini-Colloquium 
"Semiconductor-based sensors - technology, modeling, applications" 
(virtual at MIXDES), June 27, 2020
Chairs: Wladek Grabinski, Daniel Tomaszewski

10.00-10.45
Arokia Nathan "Ultralow Power, High-Resolution Sensor Interfaces"
EDS Distinguished Lecturer, Cambridge Touch Technologies, UK; E-mail: an299@cam.ac.uk
10.45-11.30
Mike Schwarz "Sensor Design – From Prototype to Series"
Robert Bosch GmbH, 72703 Reutlingen,Germany; E-mail: Mike.Schwarz@de.bosch.com
12.00-12.45
Benjamin Iñíguez "Compact Modeling and Parameter Extraction for Oxide and Organic Thin Film Transistors (TFTs) from 150K to 350K"
EDS Distinguished Lecturer, Department of Electrical, Electronics Engineering and Automatic Control Engineering, Universitat Rovira i Virgili, 43007 Tarragona, Spain; E-mail: benjamin.iniguez@urv.cat
12.45-13.30
Teoder Gotszalk " Microsystem Electronics and Photonics "
Faculty of Microsystem Electronics and Photonics, Wroclaw University of Technology, Poland; E-mail: teodor.gotszalk@pwr.edu.pl
13.30-14.15
Mina Rais-Zadeh "Phase change electro-optical devices for space applications" (recorded)
EDS Distinguished Lecturer, NASA Jet Propulsion Lab., California Institute of Techn., USA; E-mail: minar@umich.edu

Jun 8, 2020

2020 IEEE ED Poland Chapter MQ

Date
2020-06-26
Location
Virtual
Region
IEEE Region 8 (Europe, Middle East and Africa)
Contact
Krzysztof Górecki – k.gorecki@we.am.gdynia.pl
Description
Distinguished Lecturer
Arokia Nathan - Oxide Electronics Univ. Cambridge (UK)
Mina Rais-Zadeh - MEMS development at JPL (US)
Benjamin Iniguez - Universitat Rovira i Virgili, Tarragona (SP)
Teodor Gotszalk - TU Wrocław (PL)
Mike Schwarz - MEMS Design & Simulation, Bosch (D)

REGISTER at the MQ site
https://eds.ieee.org/education/distinguished-lecturer-mini-colloquia-program/upcoming-dl-and-mq-events?eid=731&m=10e18da593444dc0cb20a2f377717f95

May 6, 2020

IEEE EDS DL Series by the EDS Delhi Chapter



IEEE.org
IEEE Electronc Devices Society
IEEE Electron Device Society (EDS) Delhi Chapter – India
&
Department of Electronic Science
University of Delhi South Campus, New Delhi, India
Delhi University - Colleges, Cut off 2020, Courses, Fees, Admissions
Jointly Organizes
EDS Distinguished Lecture
(Live Session under EDS Distinguished Lecturer Program - Virtual Lectures)
Online Live Webinar Lecture Schedule (via Google Meet)
April 30, 2020 at 10:30 am (past event)
High-k Dielectric and Interface Engineering for High Performance Si/Ge MOS and FinFETs
Kuei-Shu Chang-Liao
Department of Engineering and System Science
National Tsing Hua University, Hsinchu, Taiwan
May 01, 2020 at 10:30 am  (past event)
Two-dimensional Layered Materials for Nanoelectronics
http://ap.polyu.edu.hk/ychai/images/20140716_231304.jpgYang Chai
Associate Professor, Department of Applied Physics
The Hong Kong Polytechnic University
May 05, 2020 at 01:30 pm (past event)
Introducing two-dimensional layered dielectrics in solid-state micro-electronic devices
Mario LanzaMario Lanza
Institute of Functional Nano & Soft Materials, Soochow University, Collaborative Innovation Center of Suzhou Nano Science & Technology, China
May 06, 2020 at 06:30 pm (past event)
Field Effect Transistors: From MOSFET to Tunnel-FET
Joao Antonio Martino
Professor at University of Sao Paulo, Brazil
May 08,2020 at 06:30 pm IST
Junctionless Nanowire Transistors: Electrical Characteristics and Compact Modeling
Marcelo Antonio Pavanello Centro Universitario FEI, Department of Electrical Engineering Av. Humberto de Alencar Castelo Branco, Sao Bernardo do Campo,  Brazil
May 11, 2020 at 01:30 pm IST
From CMOS to Neuromorphic Computing - A peek into the future
EEE Staff Photo Prof M De SouzaMaria Merlyne De Souza
Department of Electronic and Electrical Engineering
The University of Sheffield, United Kingdom 
May 12, 2020 at 10:30 am IST
Phase change electro-optical devices for space applications
Mina Rais-Zadeh  portraitMina Rais-Zadeh
Group Supervisor, Advanced Optical and Electromechanical Microsystems Group, Micro Device Laboratory, NASA JPL, Pasadena, CA
May 15, 2020 at 08:30 pm IST
State-of-the-Art Silicon Very Large Scale Integrated Circuits: Industrial Face of Nanotechnology
https://ecse.rpi.edu/~shur/index_files/Shur.jpgMichael S. Shur 
Electrical, Computer and Systems Engineering and Physics, Applied Physics, and Astronomy
Rensselaer Polytechnic Institute 
May 16, 2020 at 02:00 pm IST
Transparent and Flexible Large Area Electronics
Arokia  Nathan portraitArokia Nathan 
Cambridge Touch Technologies, 
University of Cambridge, United Kingdom (UK)
May 20, 2020 at 02:30 pm IST
Trends and challenges in Nanoelectronics for the next decade
Elena  Gnani portraitElena Gnani 
Department of Electrical, Electronic and Information Engineering, University of Bologna, Italy 
May 22, 2020 at 07:30 pm IST
Accelerating commercialization of SiC power electronics
Victor VeliadisVictor Veliadis
Executive Director and CTO, Power America
Professor of Electrical and Computer Engineering, 
North Carolina State University
May 27, 2020 at 07:30 pm IST
Advanced III-N Devices for 5G and Beyond
Patrick Fay
Department of Electrical Engineering, 
University of Notre Dame
More talks will be added so if you wish to attend any of these then then kindly register on:


Coordinated by:
Dr. Manoj Saxena, SMIEEE, FIETE, MNASc (India)
EDS BoG Member (2018-2020) & EDS DL
Regional Editor for South Asia, IEEE EDS Newsletter
Associate Professor, Department of Electronics 
Deen Dayal Upadhyaya College, University of Delhi 
Dwarka Sector-3, New Delhi, India; Email: msaxena@ieee.org 
Professor Mridula Gupta, SMIEEE, FIETE
Chairperson-IEEE EDS Delhi Chapter
Head, Department of Electronic Science
University of Delhi South Campus
New Delhi 110021, India