Showing posts with label Design. Show all posts
Showing posts with label Design. Show all posts

Mar 25, 2024

[OSDA 2024] 4th Workshop on Open-Source Design Automation


4th Workshop on Open-Source Design Automation
OSDA 2024
at DATE Palacio De Congresos València, Spain
25 Mar 2024

Organiser: Christian Krieg, TU Wien, Austria

OSDA intends to provide an avenue for industry, academics, and hobbyists to collaborate, network, and share their latest visions and open-source contributions, with a view to promoting reproducibility and re-usability in the design automation space. DATE provides the ideal venue to reach this audience since it is the flagship European conference in this field -- particularly poignant due to the recent efforts across the European Union (and beyond) that mandate “open access” for publicly funded research to both published manuscripts as well as software code necessary for reproducing its conclusions. A secondary objective of this workshop is to provide a peer-reviewed forum for researchers to publish “enabling” technology such as infrastructure or tooling as open-source contributions -- standalone technology that would not normally be regarded as novel by traditional conferences -- such that others inside and outside of academia may build upon it.

Agenda:

Christian Krieg; Post-Doctoral Researcher and Teacher at TU Wien
Welcome Session
Luca Carloni ;Professor at Columbia University
ESP: An Open-Source Platform for Collaborative Design of Heterogeneous Systems-on-Chip
Jean-Paul Chaput; Engineer at Sorbonne Université
Update on the Coriolis EDA Toolchain
Dirk Koch; Professor at Heidelberg University
FABulous: An embedded eFPGA Framework - an Update
Matthew Venn; Founder at YosysHQ, TinyTapeout
Demo Pitch: Tiny Tapeout
Claire Xenia Wolf; CTO at YosysHQ
Yosys
Frans Skarman PhD Student at Linköping University
Surfer -- An Extensible and Snappy Waveform Viewer

Poster Session
  • Vojtech Mrazek
    An Open-Source Automated Design Space Exploration Framework for Approximate Accelerators in FPGAs and ASICs
  • Marc Solé i Bonet, Aridane Alvarez Suarez and Leonidas Kosmidis
    The METASAT Hardware Platform v1.1: Identifying the Challenges for its RISC-V CPU and GPU Update
  • Louis Ledoux and Marc Casas
    The Grafted Superset Approach: Bridging Python to Silicon with Asynchronous Compilation and Beyond
  • Manfred Schlägl, Christoph Hazott and Daniel Große
    RISC-V VP++: Next Generation Open-Source Virtual Prototype
  • Guillem López-Paradís, Brian Li, Adrià Armejach, Stefan Wallentowitz, Miquel Moretó and Jonathan Balkind
    Using Supercomputers to Parallelize RTL Simulations
  • Davide Cieri
    Hog (HDL on git): a tool to manage HDL code on a git repository
  • Jakob Ratschenberger and Harald Pretl
    RALF: A Reinforcement Learning Assisted Automated Analog Layout Design Flow
  • Ajeetha Kumari Venkatesan, Anirudh Pradyumnan Srinivasan, Deepa Palaniappan
    Adding configurability to PySlint using TOML
  • Lucas Klemmer and Daniel Grosse
    WSVA: A SystemVerilog Assertion to WAL Compiler




Mar 17, 2024

SSCS April Technical Webinar

SSCS April Technical Webinar


Abstract: In this presentation, Matt Venn will share his experience of getting started with chip design using the free and open source tools. Going from zero to 20 chips in 3 years, there are plenty of successes and failures to share. Matt will then move on to sharing the best resources, inspirational example projects, and showcase some of his own tools. The presentation will finish with a demonstration showing just how easy and cheap it is to get your own chip manufactured today.

Biography: Matt Venn is a science & technology communicator and electronic engineer. He has been involved with open source silicon for the last 3 years and has sent 20 chips for manufacture. He has helped over 600 people learn the tools, with 300 people taking part in manufacturable designs:
  • https://zerotoasiccourse.com/
  • https://tinytapeout.com
Date: 2024-04-19 Time: 11 AM ET
Location Webinar - Online
Contact Aeisha VanBuskirk – a.vanbuskirk@ieee.org

Register Here

Jan 3, 2024

VLSID 2024 Conference


PULP Platform @pulp_platform (5h)
Cheers to 2024! The 37th International Conference on VLSI Design will start in Kolkata on Monday. @LucaBenini will give a banquet talk titled "Open Platform for the Embodied AI Era" at 7:10 PM (IST) on January 9. Check out the conference website for tutorials and schedule: https://vlsid.org

In the present era of automation and connected things, VLSI technology armed with AI and Quantum could be pivotal in changing the VLSI landscape starting from manufacturing to devices to design. To elaborate on this paradigm shift, the theme 2024 VLSI Design conference is aptly chosen to be “VLSI meets AI and Quantum for Cyber Physical Systems”.

Over a span of five-days of VLSID2024, the summit will feed brains and nurture minds with state-of-the-art exhibitors, presentations, panel discussions, innovation forums, and tutorials by established technologists.

[paper] MEMS pressure sensors

Xiangguang Han, Mimi Huang, Zutang Wu, Yi Gao, Yong Xia, Ping Yang, Shu Fan, Xuhao Lu, Xiaokai Yang, Lin Liang, Wenbi Su, Lu Wang, Zeyu Cui, Yihe Zhao, Zhikang Li, Libo Zhao
and Zhuangde Jiang
Advances in high-performance MEMS pressure sensors: design, fabrication, and packaging.
Microsyst Nanoeng 9, 156 (2023) 
DOI:10.1038/s41378-023-00620-1

1 State Key Laboratory for Manufacturing Systems Engineering, Xi’an Jiaotong University, Xi’an 710049, China
2 International Joint Laboratory for Micro/Nano Manufacturing and Measurement Technologies, Xi’an Jiaotong University, Xi’an 710049, China.
3 School of Mechanical Engineering, Xi’an Jiaotong University, Xi’an 710049, China.
4 Northwest Institute of Nuclear Technology, Xi’an 710024, China


Abstract: Pressure sensors play a vital role in aerospace, automotive, medical, and consumer electronics. Although microelectromechanical system (MEMS)-based pressure sensors have been widely used for decades, new trends in pressure sensors, including higher sensitivity, higher accuracy, better multifunctionality, smaller chip size, and smaller package size, have recently emerged. The demand for performance upgradation has led to breakthroughs in sensor materials, design, fabrication, and packaging methods, which have emerged frequently in recent decades. This paper reviews common new trends in MEMS pressure sensors, including minute differential pressure sensors (MDPSs), resonant pressure sensors (RPSs), integrated pressure sensors, miniaturized pressure chips, and leadless pressure sensors. To realize an extremely sensitive MDPS with broad application potential, including in medical ventilators and fire residual pressure monitors, the “beam-membrane-island” sensor design exhibits the best performance of 66 μV/V/kPa with a natural frequency of 11.3 kHz. In high-accuracy applications, silicon and quartz RPS are analyzed, and both materials show ±0.01%FS accuracy with respect to varying temperature coefficient of frequency (TCF) control methods. To improve MEMS sensor integration, different integrated “pressure + x” sensor designs and fabrication methods are compared. In this realm, the intercoupling effect still requires further investigation. Typical fabrication methods for microsized pressure sensor chips are also reviewed. To date, the chip thickness size can be controlled to be <0.1 mm, which is advantageous for implant sensors. Furthermore, a leadless pressure sensor was analyzed, offering an extremely small package size and harsh environmental compatibility. This review is structured as follows. The background of pressure sensors is first presented. Then, an in-depth introduction to MEMS pressure sensors based on different application scenarios is provided. Additionally, their respective characteristics and significant advancements are analyzed and summarized. Finally, development trends of MEMS pressure sensors in different fields are analyzed.

Fig: High-sensitivity MDPS, on-chip amplified MDPS, and resonant MDPS.

Acknowledgements: This study was supported in part by the National Key Research and Development Program of China (2021YFB3203200) and the Natural Scienc Foundation of Shaanxi (2022JQ-554).

Nov 10, 2023

Cutting-Edge IC Design Workshop

U.S. - Japan Collaboration Workshop
(Phase-1)
Tuesday, December 5 2023; 8:00 - 12:00 AM  (JST)
Wednesday, December 6 2023; 8:00 - 12:00 AM (JST) 
Online

The semiconductor industry is facing a number of challenges in building a stable supply chain. The importance of semiconductors was reaffirmed at the global level, and various initiatives were announced to revitalize and support the semiconductor industry, including investment in infrastructure development and human resource development for cutting-edge foundries. Against this backdrop, it is hoped that the creation of next-generation semiconductor technology and the further expansion of the industry will be achieved based on strong cooperation between Japan and the United States. As a phase 1 toward this goal, this workshop will discuss cutting-edge IC design technologies such as open source IC design, ecosystem construction, and human resource development. This workshop was supported by the U.S. Consulate in Fukuoka.

Application deadline is December 12. Please apply individually for DAY-1 and DAY-1the following form (you can also apply for only one of them).
[Participation fee] Free
[Notice] Simultaneous interpretation is available in English and at ZOOM Webinar.

DAY-1: Dec. 5th, 8:00-11:35 AM (JST)
8:00 - 8:05 Opening Remark and Overview of the Workshop, Mehdi Saligane, University of Michigan, Koji Inoue, Kyushu University
8:05 - 8:10 Welcome Remarks from the U.S. Consulate in Fukuoka
8:10 - 8:40 TBD, Steve Kosier, Skywater
8:40 - 9:10 The Emerging Ecosystem of Open-Source IC Design: IEEE SSCS Activities and Future Goals, Boris Murmann, Chair of the SSCS TC OSE, University of Hawaii
9:10 - 9:40 Human resource development for Semiconductor Technologies in Fukuoka, Koji Inoue, Fukuoka Semiconductor Reskilling Center/Kyushu University, Hideharu Kanaya, Kyushu University,
9:40 - 9:50 Break
9:50 - 10:20 Lab to Fab in the Cloud: Semiconductor Innovation at Amazon, David Pellerin, AWS 
10:20 - 10:50 TBD, Kai Yick, Google Research ML
10:50 - 11:20 Analog and Mixed-Signal IC Design Automation, David Wentzloff, University of Michigan
11:20 - 11:30 Q&A + Panel Discussion
11:30 - 11:35 Conclusion, Mehdi Saligane, University of Michigan

DAY-2: Dec. 6th, 8:00-11:30 AM (JST)
8:00 - 8:05 Opening Remark and Overview of the Workshop, Mehdi Saligane, University of Michigan, Koji Inoue, Kyushu University
8:05 - 8:35 Innovation by Collaboration: CHIPS Alliance, Rob Mains, CHIPS Alliance, Linux Foundation 
8:35 - 9:05 Developing CMOS+X Platforms for Artificial Intelligence and Beyond, Brian Hoskins, NIST 
9:05 - 9:35 Agile-X: Agile Chip Design and Fabrication Platform, Makoto Ikeda, University of Tokyo
9:35 - 9:45 Break
9:45 - 10:15 The future of semiconductor : chips and chiplets, Dan J. Dechene, IBM Research
10:15 - 10:45 AI Chip Design Center – open hub for chip innovation -, Kunio Uchiyama, National Institute of Advanced Industrial Science and Technology  
10:45 - 11:15 Democratizing EDA Tooling and Chip Design, Johan Euphrosine, Google (Tentative)
11:15 - 11:25 Q&A + Panel Discussion
11:25 - 11:30 Conclusion and Overview of the phase-2 workshop activities, Mehdi Saligane, University of Michigan, Koji Inoue, Kyushu University

[お問い合わせ] ic-design-ws 'at' slrc.kyushu-u.ac.jp ( 'at' を @ で置き換えてください)

Nov 2, 2023

[paper] ChipNeMo

Mingjie Liu, Teo Ene, Robert Kirby, Chris Cheng, Nathaniel Pinckney, Rongjian LiangJonah Alben, Himyanshu Anand, Sanmitra Banerjee, Ismet Bayraktaroglu, Bonita Bhaskaran Bryan Catanzaro, Arjun Chaudhuri, Sharon Clay, Bill Dally, Laura Dang, Parikshit Deshpande Siddhanth Dhodhi, Sameer Halepete, Eric Hill, Jiashang Hu, Sumit Jain, Brucek Khailany Kishor Kunal, Xiaowei Li, Hao Liu, Stuart Oberman, Sujeet Omar, Sreedhar Pratty, Ambar Sarkar Zhengjiang Shao, Hanfei Sun, Pratik P Suthar, Varun Tej, Kaizhe Xu, Haoxing Ren
ChipNeMo: Domain-Adapted LLMs for Chip Design
arXiv:2311.00176 [cs.CL]
DOI: 10.48550/arXiv.2311.00176

* NVIDIA

Abstract: ChipNeMo aims to explore the applications of large language models (LLMs) for industrial chip design. Instead of directly deploying off-the-shelf commercial or open-source LLMs, we instead adopt the following domain adaptation techniques: custom tokenizers, domain-adaptive continued pretraining, supervised fine-tuning (SFT) with domain-specific instructions, and domain-adapted retrieval models. We evaluate these methods on three selected LLM applications for chip design: an engineering assistant chatbot, EDA script generation, and bug summarization and analysis. Our results show that these domain adaptation techniques enable significant LLM performance improvements over general-purpose base models across the three evaluated applications, enabling up to 5x model size reduction with similar or better performance on a range of design tasks. Our findings also indicate that there’s still room for improvement between our current results and ideal outcomes. We believe that further investigation of domain-adapted LLM approaches will help close this gap in the future.
Fig: LLM script generator integration with EDA tools

Acknowledgements: The authors would like to thank: NVIDIA IT teams for their support on NVBugs integration; NVIDIA Hardware Security team for their support on security issues; NVIDIA NeMo teams for their support and guidance on training and inference of ChipNeMo models; NVIDIA Infrastructure teams for supporting the GPU training and inference resources for the project; NVIDIA Hardware design teams for their support and insight.

Jul 31, 2023

[book] Negative Capacitance Field Effect Transistors


Negative Capacitance Field Effect Transistors
Physics, Design, Modeling and Applications


Edited By Young Suh Song, Shubham Tayal, Shiromani Balmukund Rahi, Abhishek Kumar Upadhyay


Pages 63 Color & 7 B/W Illustrations
ISBN 9781032445311 176 Sept. 29, 2023 by CRC Press


Description
This book aims to provide information in the ever-growing field of low-power electronic devices and their applications in portable device, wireless communication, sensor, and circuit domains. Negative Capacitance Field Effect Transistor: Physics, Design, Modeling and Applications, discusses low-power semiconductor technology and addresses state-of-art techniques such as negative-capacitance field-effect transistors and tunnel field-effect transistors. The book is broken up into four parts. Part one discusses foundations of low-power electronics including the challenges and demands and concepts like subthreshold swing. Part two discusses the basic operations of negative-capacitance field-effect transistor (NC-FET) and Tunnel Field-effect Transistor (TFET). Part three covers industrial applications including cryogenics and biosensors with NC-FET. This book is designed to be one-stop guidebook for students and academic researchers, to understand recent trends in the IT industry and semiconductor industry. It will also be of interest to researchers in the field of nanodevices like NC-FET, FinFET, Tunnel FET, and device-circuit codesign.

Table of Contents
Chapter 1 Recent Challenges in IT and Semiconductor Industry: From Von Neumann Architecture to the Future
Young Suh Song, Shiromani Balmukund Rahi, Navjeet Bagga, Sunil Rathore, Rajeewa Kumar Jaisawal, P. Vimala, Neha Paras, K. Srinivasa Rao
Chapter 2 Technical Demands of Low-Power Electronics
Soha Maqbool Bhat, Pooran Singh, Ramakant Yadav, Shiromani Balmukund Rahi, Billel Smaani, Abhishek Kumar Upadhyay, Young Suh Song
Chapter 3 Negative capacitance Field Effect Transistors: Concept and Technology
Ball Mukund Mani Tripathi
Chapter 4 Basic Operation Principle of Negative Capacitance Field Effect Transistor
Malvika, Bijit Choudhuri, Kavicharan Mummaneni
Chapter 5 Basic Operational Principle of Anti-ferroelectric Materials and Ferroelectric Materials
Umesh Chandra Bind, Shiromani Balmukund Rahi
Chapter 6 Basic Operation Principle of Optimized NCFET: Amplification Perspective
S. Yadav, P.N Kondekar, B. Awadhiya
Chapter 7 Spin Based Magnetic Devices With Spintronics
Asif Rasool, Shahnaz kossar, R.Amiruddin
Chapter 8 Mathematical Approach for Future Semiconductor Roadmap
Shiromani Balmukund Rahi,Abhishek Kumar Upadhyay, Young Suh Song, Nidhi Sahni, Ramakant Yadav, Umesh Chandra Bind,Guenifi Naima,Billel Smaani,Chandan Kumar Pandey,Samir Labiod, T.S. Arun Samul,Hanumanl Lal, H. Bijo Josheph
Chapter 9 Mathematical Approach for Foundation of Negative Capacitance Technology
Shiromani Balmukund Rahi,Abhishek Kumar Upadhyay, Young Suh Song, Nidhi Sahni, Ramakant Yadav, Umesh Chandra Bind,Guenifi Naima,Billel Smaani,Chandan Kumar Pandey,Samir Labiod, T.S. Arun Samul,Hanumanl Lal, H. Bijo Josheph


Jun 9, 2023

[Workshop] Open Source PDKs and EDA


RIHGA Royal Hotel Kyoto, Horikawa Shiokoji, Shimogyo ku, Kyoto 600 8237, Japan.
Date & Time: 5:30pm.-7:15pm on June 11 (Sun), 2023

Since its launch in 2020, the Open MPW shuttle program has received over 500 project submissions spanning 9 shuttles. This workshop will explore various topics related to designers' experiences, including measured results, foundry perspectives, and governmental expectations.

Organizers: 
  • Makoto Ikeda (The University of Tokyo)
  • Mehdi Saligane (University of Michigan)
Program:
  1. Design experience: “The Journey of Two Novice LSI Enthusiasts: Tape-Out of CPU+RAM in Just One Month”, Kazuhide Uchiyama, University of Electro-Communications and Yuki Azuma, University of Tsukuba
  2. From Zero to 1000 Open Source Custom Designs in Two Years, Mohamed Kassem, Co-founder and CTO, Efabless
  3. The SKY130 Open Source PDK: Building an Open Source Innovation Ecosystem, Steve Kosier, Skywater technology
  4. Open Source Chip Design on GF180MCU – A foundry perspective, Karthik Chandrasekaran, Global Foundries
  5. Japan Foundries' Perspectives on Silicon design democratization, Shiro Hara, Minimal Fab & AIST
  6. Google's perspective on Open source PDKs, Open source EDA tools, and OpenMPW shuttle program, Johan Euphrosine and Tim Ansell, Google
  7. The Nanofabrication Accelerator Project, Matthew Daniels, NIST
  8. Japanese government perspective on Silicon design democratization, Yohei Ogino, The Ministry of Economy, Trade and Industry METI
VLSI Symposium Workshop1 "Open Source PDKs and EDA" Audience


May 17, 2023

[chapter] Systematic Design of Analog CMOS Circuits with Lookup Tables

Systematic Design of Analog CMOS Circuits with Lookup Tables
By Paul G. A. Jespers, Université Catholique de Louvain, Belgium

in Foundations and Trends in Integrated Circuits and Systems
Vol. 2: No. 3, pp 193-243. http://dx.doi.org/10.1561/3500000004

Publication Date: 08 May 2023
© 2023 P. G. A. Jespers*

ABSTRACT The idea underlying the methodology described in this monograph consists in the use of a set of Lookup Tables embodying device data extracted prior from systematic runs done once and for all using an advanced circuit simulator, the same as used for final design verifications. In this way, all parameters put to use during the sizing procedure incorporate not only the bearings of bias conditions and geometry, but also every second-order effect present in the simulator’s model, in particular short-channel effects. Consequently, the number of verification simulations one has to perform is not only substantially reduced, but the designer may concentrate on actual design strategies without being bothered by inconsistencies caused by poor models or inappropriate parameters.

Fig: The drain current ID versus the gate-to-source voltage VGS (plain lines) compared to the EKV best fit (+). The other lines represent the exponential and quadratic approximations.

∗The author acknowledges the kind support of Prof. Boris Murmann in writing this monograph.

Nov 27, 2021

[paper] Bridging the gap between design and simulation of low voltage CMOS circuits

C. M. Adornes, D. G. Alves Neto, M. C. Schneider and C. Galup-Montoro
Bridging the gap between design and simulation of low voltage CMOS circuits
2021 IEEE Nordic Circuits and Systems Conference (NorCAS), 2021, pp. 1-5,
DOI: 10.1109/NorCAS53631.2021.9599867

Abstract: This work proposes a simplified MOSFET model based on the Advanced Compact MOSFET (ACM) model, which contains only four parameters to assist the designer in understanding how the main MOSFET parameters affect the design. The 4-parameter model was implemented in Verilog-A to simulate different circuits designed with the ACM model. A CMOS inverter and a ring oscillator were designed and simulated, either using the 4-parameter ACM model or the BSIM model. The simulation results demonstrate that the 4-parameter model is very suitable for ultra-low-voltage (ULV) modeling. In the ultra-low-voltage domain, some of the secondary effects of the MOSFET are not relevant and thus not included in the 4-parameter model. A simplified MOSFET model for the ULV domain is of great importance to applications such as energy harvesting, sensor nodes for the Internet of Things, and always-on circuits.

Acknowledgment: The authors would like to thank the Brazilian agencies CAPES, finance code 001, and CNPq for supporting this work.

REF:
[1] A. I. A. Cunha, M. C. Schneider and C. Galup-Montoro, "An MOS Transistor Model for Analog Circuit Design", IEEE J. Solid-State Circuits, vol. 33, no. 10, pp. 1510-1519, October 1998
[2] C. Galup-Montoro and M. C. Schneider, "The compact all-region MOSFET model: theory and applications", IEEE 16th International New Circuits and Systems Conference (NEWCAS), pp. 166-169, June 2018
[3] M. C. Schneider and C. Galup-Montoro, CMOS Analog Design Using All-Region MOSFET Modeling, Cambridge University Press, 2010
[4] C. Galup-Montoro and M. C. Schneider, MOSFET modeling for circuit analysis and design, World Scientific, 2007
[5] Verilog-A Reference Manual, Agilent Technologies, 2004
[6] 0. F. Siebel, "Um modelo eficiente do transistor MOS para o projeto de circuitos VLSI," Universidade Federal de Santa Catarina, Florianopolis, 2007
[7] F. N. Fritsch, R. E. Shafer and W. P. Crowley, "Algorithm 443: Solution of the transcendental equation wew=x," Commun. ACM, vol. 16, no. 2, pp. 123-124, 1973
[8] O. F. Siebel, M. C. Schneider and C. Galup-Montoro, "MOSFET threshold voltage definition, extraction and some applications," Microelectronics Journal, vol. 43, no. 5, pp. 329-336, May 2012
[9] G. Hiblot. DIBL-Compensated Extraction of the Channel Length Modulation Coefficient in MOSFETS. IEEE Transactions on Electron Devices, vol. 65, no. 9, pp. 4015-4018, 2018
[10] BSIM4v4.5.0 Technical Manual, Department of Electrical Engineering and Computer Science, UC Berkeley, Berkeley, CA, USA. 2004
[11] Y. Tsividis and C. McAndrew, Operation and Modeling of the MOS Transistor, Oxford Univ. Press, 2011
[12] J. V. T. Ferreira, C. Galup-Montoro, "Ultra-low-voltage CMOS ring oscillators. Electronics Letters," IET, v. 55, n. 9, p. 523-525,2019
[13] E. M. Camacho-Galeano, C. Galup-Montoro and M. C. Schneider, "A 2-nW 1.1.-V self biased current reference in CMOS technology," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 52, no. 2, pp. 61-65, 2005
[14] E. Bolzan, E. B. Storck, M. C. Schneider and C. Galup-Montoro, "Design and testing of a CMOS SelfBiased Current Source," 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 382-385, 2019

May 25, 2021

Circuit Design and Simulation Marathon using eSIM

 

Indian Institute of Technology, Bombay

We are happy to announce the first ever #Circuit #Design and #Simulation #Marathon using #eSim! This event is jointly organized by #FOSSEE and VLSI System Design. The FOSSEE project developed at Indian Institute of Technology, Bombay is powered by MINISTRY OF EDUCATION, GOVERNMENT OF INDIA.

To know more about the Circuit Design and Simulation Marathon, please visit https://hackathon.fossee.in/esim/

Important dates:
>> Registration: 21 May 2021 - 15 June 2021
>> Marathon Launch : 17 June 2021

Mar 17, 2021

[Workshop] Democratizing IC Design, April 7th, 2021

Solid-State Circuits Directions Workshop:
Democratizing IC Design
Wednesday, April 7th, 2021 at 7:00 AM PT / 10:00 AM ET
This event is free and open to all

EVENT DESCRIPTION
Solid-State Circuits Directions (SSCD) is a new technical committee within the IEEE Solid-State Circuits Society (related article). Its charter is to promote forward-looking topics, build new communities and stimulate interaction with others. Following SSCD’s inaugural event on hardware security, the upcoming workshop will look at the new movement toward an open-source ecosystem for integrated circuit design.

Over the past several decades, society has strongly benefited from free and open-source software. More recently, the open-source spirit has expanded to hardware and has energized a new maker community that tinkers with embedded systems at the printed circuit board level. Groundbreaking developments have now also opened the door toward democratizing integrated circuit design.

Last year, Google, SkyWater and efabless have partnered to launch a shuttle program based on SkyWater’s SKY130 open-source process (130 nm CMOS). This technology is offered to the open community along with a complete design flow to enable designers to implement their ideas. This workshop will provide an overview of this program and highlight upcoming opportunities to benefit from it. Finally, it will showcase specific design work delivered by the community members and articulate a call to action for volunteers to design, teach and mentor.

AGENDA
7:00 AM PT- Welcome & Introductions (Boris Murmann, Stanford University)
7:05 AM PT- Fully open source manufacturable PDK for a 130nm process (Tim Ansell, Google)
7:35 AM PT- 45 Chips in 30 Days: Open Source ASIC at its best! (Mohamed Kassem, efabless)
7:55 AM PT- Design 1: Open Source eFPGA implementation in SKY130 (Xifan Tang, University of Utah)
8:25 AM PT- Design 2: Amateur Radio Satellite Transceiver (Thomas Parry, SystematIC Design)
8:55 AM PT- Call to Action: Need volunteers to design, teach and mentor
9:00 AM PT- Adjourn

Aug 25, 2020

Analog IC Designer's Handbook

by Jean-Francois Debroux
 
Abstract: Analog IC design is one of the particular design activities where designers get feedback on their choices only months after they finish their design and where the cost of even the smallest design change is huge.
This has historically brought the need for new tools such as SPICE, the ancestor of almost all the electric simulators, so as to give feedback on the design choices before actually getting the prototypes. This should also have deeply impacted the design methods, and it has, but the availability of simulators has finally allowed the old “try and fix” method not only to survive but also to stay very popular.
If tools such as electric simulators have gained popularity in most electronic design fields, even out of the IC design world, methods such as the TOP-DOWN approach are not as popular as they should be, especially in the analog design community, even in the analog IC design microcosm. This is probably because this method is felt as difficult to use practically even though most designers agree that it is the right approach.
The goal of this book is to show that the TOP-DOWN approach for analog design is not only valid but that it is one of the most powerful available methods to create good analog design without sacrificing the time to market. This method creates faster and better designs but requires a good understanding of the method itself, of course, but also of the underlying techniques and of the basic design elements.
After a general introduction of the TOP-DOWN method goals and principles in the first part, the second part presents and details analog IC design elements from components to basic building blocks with a strong emphasis on practical aspects. Various additional design techniques are then detailed in the third part. The reader is then ready for the main course, a series of design examples based on the TOP-DOWN method that are grouped in the fourth part. These examples are processed the way they are in real life, from specification to implementation, from general considerations down to implementation details. Analysis of existing circuits is useful for learning but real life design is synthesis, not analysis.
Finally, the fifth part introduces or reminds useful basic concepts and presents the notation in use through the book.
The methods and techniques described in this book have been used by the author through 25 years of analog and mixed signal ICs design experience in various application fields including RF and sensor signal conditioning for various markets such as industrial, automotive and aerospace. The author feels that the method he presents in this book can help many analog electronic designers in their day to day work and hopes it will bring both a deeper understanding of design and a broader view over design activities. [read more...]

Experience: See  Jean-Francois Debroux profile on LinkedIn

Jul 20, 2020

[C4P] Advanced FETs: Design, Fabrication and Applications

Call for Papers: Special MDPI  Issue 
"Advanced Field Effect Transistors: Design, Fabrication and Applications"
Deadline for manuscript submissions: 31 July 2021.

Dear Colleagues,
Planar MOS Field Effect Transistors (MOSFETs) were invented by Atalla and Kahng in 1959. After a decade, the MOSFETs entered mass production, as basic building blocks of P-, N-, and CMOS integrated circuits (ICs). Until the end of the twentieth century, MOSFET performance was largely improved by the implementation of so-called scaling rules. An exponential growth in the time of the transistor number per chip (observation formulated as Moore law) was achieved. This, together with advantageous characteristics and a nice feature of the planar MOSFETs allowing one to design the ICs by defining a width/length ratio, led to the great success of the CMOS technology on Si and SOI substrates.
However, starting from the 90 nm node, it has been observed that the standard scaling does not sufficiently translate into MOSFET performance improvement. Moreover, some device characteristics become degraded, e.g. gate leakage, channel leakage, variability and reliability. This has led to the development of preventative measures (e.g. high-k dielectrics) or performance boosters (e.g. channel strain engineering and channel materials). Furthermore, 2D and 3D multi-gate FETs were introduced to improve gate control over the channel and increase the channel aspect ratio. Multi-gate FETs are the only option for the 5nm node, which is expected soon, whereas they will have to be replaced by surrounding gate FETs for the 3nm node. For the past few years, the attention of researchers has been attracted by steep-subthreshold slope devices, enabling the reduction of supply voltage. A need for devices for quantum computing has appeared. FETs and HEMTs, for very high frequency applications, GaN, SiC and FETs for high voltage, high power, high temperature applications, and many other FET types, are in use or under development as a micro- and nanoelectronics reply to electronics needs in different domains.
There are many issues regarding the design, fabrication and applications of advanced field effect transistors. It is my pleasure to invite you to share your expertise in this Special Issue. Full papers, communications and reviews are all welcome.

Dr. Daniel Tomaszewski, ITE, Warsaw (PL)
Special Issue Guest Editor

[read more...]

Jun 22, 2017

[paper] Design Strategies for Ultralow Power 10nm FinFETs

Design Strategies for Ultralow Power 10nm FinFETs
Abhijeet Walkeaa, Garrett Schlenvogtbb, Santosh Kurinecaa
aDepartment of Electrical & Microelectronic Engineering, RIT, New York, USA
bTCAD Application Engineer, Silvaco

Received 12 June 2017, Accepted 19 June 2017, Available online 20 June 2017

Abstract: In this work, new design strategies for 10nm node NMOS bulk FinFET transistors are investigated to meet low power (LP) (20pA/μm< IOFF <50pA/μm) and ultralow power (ULP) (IOFF <20pA/μm) requirements using three dimensional (3D) TCAD simulations. The punch-through stop implant, source and drain junction placement and gate workfunction are varied in order to study the impact on the OFF-state current (IOFF), transconductance (gm), gate capacitance (Cgg) and intrinsic frequency (fT). It is shown that the gate length of 20nm for the 10nm node FinFET can meet the requirements of LP transistors and ULP transistors by source-drain extension engineering, punch-through stop doping concentration, and choice of gate workfunction.

[read more https://doi.org/10.1016/j.sse.2017.06.012]

Feb 7, 2016

Device to GDSII for IC Design Training

Hands on Training Program on “Device to GDSII for IC Design”
on 22-27 Feb 2016
Organized by VLSI Division of School of Electronics Engineering
Vellore Institute of Technology, Near Katpadi Rd Vellore, Tamil Nadu - 632014


The relentless march fast of the CMOS has slowed down and the semiconductor industry is looking for novel and innovative devices. Many novel devices are being explored currently. TCAD and Cadence tool allows us to generate new structures, circuits and analyze its performance. Unlike other circuit simulators, TCAD and Cadence needs a special training. This hands on training addresses this gap.

Target Audience: Faculty, students and research scholars from various engineering colleges of India. The number of participants is limited to 40. 

Topics to ďe addressed:

Using TCAD:
  • Structure Creation, Simulation and Device Simulation 
  • Process Simulation 
  • Multi-gate Transistors 
  • Radiation study on devices and circuits
Using Cadence: 
  • RTL Design and Simulation 
  • Synthesis and low power synthesis Using RTL Compiler 
  • Physical aware synthesis and DFT 
  • Block and Top Level P&R Using SOC Encounter 
  • STA Using Timing Engine