Showing posts with label Coplanar waveguides. Show all posts
Showing posts with label Coplanar waveguides. Show all posts

Feb 9, 2021

[paper] On-Chip Coplanar Waveguides

José Valdés-Rayón, Roberto S. Murphy-Arteaga and Reydezel Torres-Torres; 
Determination of the Contribution of the Ground-Shield Losses 
to the Microwave Performance of On-Chip Coplanar Waveguides 
IEEE Transactions on MTT; Feb.3, 2021 
DOI: 10.1109/TMTT.2021.3053548 
* National Institute of Astrophysics, Optics and Electronics (INAOE), Department of Electronics, Tonantzintla, Puebla 72840, Mexico.

Abstract: In this article, we characterize and model two parasitic effects that become apparent in the performance of coplanar waveguide interconnects in CMOS. One is the transverse resistance introduced by a patterned ground shield in coplanar waveguide interconnects, which significantly contributes to the shunt losses. The other one is the parasitic coupling between the input and output ports through the ground shield. The latter effect is particularly accentuated in relatively short lines and complicates the determination of the propagation constant using line-line algorithms at several tens of gigahertz. We demonstrate that using the proposed methodology, excellent model-experiment correlation can be achieved in the modeling of these types of interconnects up to at least 60 GHz.

Funding: CONACyT-Mexico

Jul 25, 2017

[paper] Compact On-Wafer Test Structures for Device RF Characterization

B. Kazemi Esfeh, K. Ben Ali and J. P. Raskin IEEE Fellow
Compact On-Wafer Test Structures for Device RF Characterization
in IEEE TED, vol. 64, no. 8, pp. 3101-3107, Aug. 2017
doi: 10.1109/TED.2017.2717196

Abstract: The main objective of this paper is to validate the radio frequency (RF) characterization procedure based on compact test structures compatible with 50um pitch RF probes. It is shown that by using these new test structures, the layout geometry and hence the on-chip space consumption for complete sets of passive and active devices, e.g., coplanar waveguide transmission lines and RF MOSFETs, is divided by a factor of two. The validity domain of these new compact test structures is demonstrated by comparing their measurement results with classical test structures compatible with 100–150um pitch RF probes. 50um -pitch de-embedding structures have been implemented on 0.18um RF silicon-on-insulator (SOI) technology. Cutoff frequencies and parasitic elements of the RF SOI transistors are extracted and the RF performance of trap-rich SOI substrates is analyzed under small- and large-signal conditions [read more...]