Mar 18, 2024
[paper] Symmetric BSIM-SOI
Jan 8, 2024
[paper] Compact Model of Graphene FETs
1 Departament d’Enginyeria Electrònica, Escola d’Enginyeria, UAB, 08193 Bellaterra, Spain
2 Graphenea Semiconductor SLU, 20009 San Sebastián, Spain.
Abstract: The main target of this article is to propose for the first time a physics-based continuous and symmetric compact model that accurately captures I–V experimental dependencies induced by geometrical scaling effects for graphene field-effect transistor (GFET) technologies. Such a scalable model is an indispensable ingredient for the boost of large-scale GFET applications, as it has been already proved in solid industry-based CMOS technologies. Dependencies of the physical model parameters on channel dimensions are thoroughly investigated, and semi-empirical expressions are derived, which precisely characterize such behaviors for an industry-based GFET technology, as well as for others developed in the research laboratory. This work aims at the establishment of the first industry standard GFET compact model that can be integrated in circuit simulation tools and, hence, can contribute to the update of GFET technology from the research level to massive industry production.
Fig: Graphenea GFET schematic cross-section not drawn to scale. Graphene under metal contacts is not shown.The drain current has explicit derivation in respect to Qgr, where Qt and Qp(n) are the transport sheet and p(n)-type charges, respectively; Vc is the chemical potential, h is the reduced Planck constant, uf is the Fermi velocity, e is the electron charge, and k is a coefficient. Qt and, thus, ID can be calculated according to Vc polarity at source (Vcs) and drain (Vcd), respectively. Hence, at n-type region where Vcs, Vcd > 0 and Qp = 0
Acknowledgements: This work was supported in part by the European Union’s Horizon 2020 Research and Innovation Program GrapheneCore3 under Grant 881603; in part by the Ministerio de Ciencia, Innovación y Universidades under Grant RTI2018-097876-B-C21 (MCIU/AEI/ FEDER, UE), Grant FJC2020-046213-I, and Grant PID2021-127840NBI00 (MCIN/AEI/FEDER, UE); in part by the European Union Regional Development Fund within the Framework of the ERDF Operational Program of Catalonia 2014–2020 with the Support of the Department de Recerca i Universitat, with a grant of 50% of Total Cost Eligible; and in part by the GraphCAT Project under Grant 001-P-001702.
Oct 23, 2023
[paper] Lorentzian noise spectra in compact models
* School of Electrical & Computer Engineering, Technical University of Crete (TUC), GR-73100 Chania, Greece European University on Responsible Consumption and Production (EURECA-PRO) (Joint affiliation)
† Institute of Electronic Structure and Laser, Foundation for Research and Technology-Hellas (IESL-FORTH), GR-71110 Heraklion, Greece
Feb 26, 2023
[paper] Fast and Expandable ANN-Based Extraction
Mar 2, 2022
[paper] Circuit-Based Compact Model of Electron Spin Qubit
University of Modena and Reggio Emilia, Modena (IT)
Mar 1, 2022
[paper] Multi-Segment TFT Compact Model for THz Applications
1 RPI, Troy, NY 12180, USA
2 Norwegian University of Science and Technology, Trondheim, Norway
3 Electronics of the Future, Inc., USA
(b) equivalent circuit for each segment including leakage components
Feb 2, 2022
[paper] Modeling of SIC VDMOS FET
∗Department of Electrical Engineering, IIT Kanpur (IN)
†Keysight Technologies (J)
Jan 27, 2022
[paper] Automatic Parameter Extraction of MOSFET Compact Models
1 Infineon Technologies AG, Munich (D)
2 Bundeswehr University Munich (D)
DEpred reaches the target 50% faster.
Dec 8, 2021
[paper] Analytical Compact Model Of Cylindrical Junctionless Nanowire FETs
[paper] Automated Compact Model Parameter Extraction
∗ Universitat der Bundeswehr Munchen, Neubiberg, Germany
† Infineon Technologies AG, Neubiberg, Germany
Nov 15, 2021
[paper] Verilog-A Compact MTJ Model
Oct 21, 2021
[paper] Charge-based Modeling of FETs
EDLab, EPFL, Lausanne (CH)
Oct 20, 2021
[paper] Compact model of 3D NAND
ISRC and School of Electrical Engineering and Computer Science, Seoul National University, (KR)
Jul 26, 2021
[paper] VNWFET Including Tied Compact Model
2 University of Bordeaux, CNRS UMR 5218, Bordeaux INP Talence, Bordeaux, France
3 Université de Toulouse, LAAS, CNRS, INP Toulouse, Toulouse, France
4 Institute of Industrial Science, LIMMS-CNRS/IIS, The University of Tokyo, Japan
Jul 21, 2021
[paper] 11.8 GHz Fin Resonant Body Transistor
May 10, 2021
[paper] Compact Model for SiC Power MOSFETs
May 4, 2021
[Si2 CMC] to Standardize SPICE Model for SiC MOSFET
The Compact Model Coalition (CMC) working group of the Silicon Integration Initiative (SI2) has agreed to standardize a model for the behaviour of a silicon-carbide MOSFET.
Apr 15, 2021
[paper] GaN-HEMT Compact Model
1 Centre for Advanced Low-Carbon Propulsion Systems, Coventry University, Coventry CV1 2TL, UK
2 Power Electronics, Machines and Control Group, University of Nottingham, Nottingham NG7 2RD, UK;
3 Laboratoire d’Electrotechnique et d’Electronique de Puissance, Université de Lille, France;
Mar 2, 2021
[paper] Predictive Hot-Carrier Aging Compact Model
2Department of Electrical Engineering (ESAT), KU Leuven, Leuven (B)
3Institute for Microelectronics (IuE), TU Wien, Vienna (A)
4Ioffe Physical-Technical Institute of the Russian Academy of Sciences, Saint Petersburg (RU)
5Department of Electronics and Informatics (ETRO/VUB), Brussels (B)