[paper] Generalized EKV Charge-based MOSFET Model

A Generalized EKV Charge-based MOSFET Model Including Oxide and Interface Traps

Chun-Min Zhang^a,  Farzan Jazaeri^a,  Giulio Borghello^b,  Serena Mattiazzo^c,  Andrea Baschirotto^d

and Christian Enz^a

Solid-State Electronics

Available online 7 January 2021, 107951

Open Access under a Creative Commons License

DOI: 10.1016/j.sse.2020.107951

a Integrated Circuits Laboratory (ICLAB), École Polytechnique Fédérale de Lausanne (EPFL), Neuchâtel 2000, Switzerland

b Department of Experimental Physics, CERN, Geneva 1211, Switzerland

c Department of Information Engineering, INFN Padova and University of Padova, Padova 35131, Italy

d Microelectronic Group, INFN Milano-Bicocca and University of Milano-Bicocca, Milano 20126, Italy

Abstract: This paper presents a generalized charge-based EKV MOSFET model that includes the effects of trapped charges in the bulk oxide and at the silicon/oxide interface. It is shown that in the presence of oxide- and interface-trapped charges, the mobile charge density can still be linearized but with respect to both the surface potential and the channel voltage. This enables us to derive closed-form expressions for the mobile charge density and the drain current. These simple formulations demonstrate the effects of charge trapping on MOSFET characteristics and crucial device parameters. The proposed charge-based analytical model, including the effect of velocity saturation, is successfully validated through measurements performed on devices from a 28nm bulk CMOS technology. Ultrahigh total ionizing doses up to 1 Grad (SiO2) are applied to generate oxide-trapped charges and activate the passivated interface traps. Despite a small number of parameters, the model is capable of accurately capturing the measurement results over a wide range of device operation from weak to strong inversion. Explicit expressions of device parameters also allow for the extraction of the oxide- and interface-trapped charge density.

Fig: Energy band diagrams illustrating interface charge trapping in bulk n- (a) and pMOSFETs (b) in inversion. The quasi-Fermi level of the minority carriers, 𝐸𝐹𝑛 or 𝐸𝐹𝑝, is split from that of the majority carriers 𝐸𝐹 by the channel voltage 𝑉𝑐ℎ

Acknowledgements: The authors would like to thank the EP-ESE group at CERN, especially Dr. Federico Faccio, for the continuous support in radiation measurements and the interesting discussions about data analysis. This work was supported in part by the Swiss National Science Foundation (SNSF) through the GigaradMOST project under grant number 200021_160185 and in part by the Istituto Nazionale di Fisica Nucleare (INFN) through the ScalTech28 Project.

[paper] FD-SOI CMOS RF FoM

28-nm FD-SOI CMOS RF Figures of Merit Down to 4.2 K

Lucas Nyssens¹ (Graduate Student Member, IEEE), Arka Halder¹, Babak Kazemi Esfeh¹,
Nicolas Planes², Denis Flandre¹ (Senior Member, IEEE), Valeriya Kilchytska¹
and Jean-Pierre Raskin¹ (Fellow, IEEE)
IEEE J-EDS, vol. 8, pp. 646-654, 2020,
DOI: 10.1109/JEDS.2020.3002201

¹UCL, 1348 Louvain-la-Neuve (B) ²ST-Microelectronics, 38920 Crolles (F)

Abstract: This work presents a detailed RF characterization of 28nm FD-SOI nMOSFETs at cryogenic temperatures down to 4.2K. Two main RF Figures of Merit (FoMs), i.e., current-gain cutoff frequency (f_T) and maximum oscillation frequency (f_max), as well as parasitic elements of the small-signal equivalent circuit, are extracted from the measured S-parameters. An improvement of up to ∼130GHz in f_T and ∼75GHz in f_max is observed for the shortest device (25nm) at low temperature. The behavior of RF FoMs versus temperature is discussed in terms of small-signal equivalent circuit elements, both intrinsic and extrinsic (parasitics). This study suggests 28nm FD-SOI nMOSFETs as a good candidate for future cryogenic applications down to 4.2K and clarifies the origin and limitations of the performance.

FIG: Small-signal equivalent circuit of the RF MOSFETs

Aknowledgement: This work was supported in part by Eniac “Places2Be” and in part by Ecsel “Waytogofast” Projects. The work of Lucas Nyssens was supported by the Fonds de la Recherche Scientifique - FNRS. This paper is based on a paper entitled “28 FDSOI RF Figures of Merit Down to 4.2 K,” presented at the 2019 IEEE S3S Conference.

IBM, GF, and Samsung offer a glimpse of chipmaking's future

Below is a slide showing GF' process tech roadmap for the next little while:

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IBM 28nm CMOS Technology

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