Tuesday, 25 April 2017

[mos-ak] [C4P] IJHSES / MOS-AK Special Issue

The IJHSES Call for Papers

Special Issue on Advances in the Compact/SPICE Modeling

and its Verilog-A Standardization


Compact/SPICE models for circuit level simulation are essential element of supporting CAD/EDA tools for advanced integrated circuit designs. Rapid mainstream CMOS technology expansion and its scaling into the nanometer regime demands development of a fully physical as well as technology predictive compact/SPICE models for circuit simulation which provides adequate, full range DC, AC, RF, and noise characteristics and its geometry, bias, temperature scaling. These tasks becomes a major R&D challenge. Fast new technology nodes developments also impose new challenges on the compact/SPICE models maintenance and development as well as on its Verilog-A standardization for the model implementation, validation and dissemination.


Standard, core compact models should include and update noise/mismatch and reliability/variability models as well as proximity effects to adequately model nanoscale devices and technologies including nonclassical MOSFETs, multigate FinFETs and nanowire FETs partially/fully-depleted ultra thin body (UTB) SOI, and thin-film transistors (TFTs). High-frequency, high-voltage high-power, high-temperature devices have been extensively investigated, and their compact models to be reviewed, too. Heterogeneous integration opens a new perspectives to the CMOS platform to integrate different materials (III-V/Ge channel, organic and different source/drain injection mechanisms (Schottky-barrier, tunneling, junctionless FETs, and others) and new nonclassical devices, high GHz/THz range detectors, Bio/Med sensors, actuators, MEMS, among others, to support emerging device in future VLSI, IoT applications and beyond.


Therefore, there is an emerging need for an new special issue to review status, challenge and advancement in the compact/SPICE modeling for nanoscaled and emerging technologies as well as beyond. The IJHSES Editors seek original manuscripts for a special issue on advanced in the Compact/SPICE Modeling and its Verilog-A standardization.


Topics to be covered include the following, but are not limited to:

  • Advances in semiconductor technologies and processing

  • Compact Modeling (CM) of the electron devices

  • Verilog-A language for CM standardization

  • New CM techniques and extraction software

  • FOSS TCAD/EDA modeling and simulation

  • CM of passive, active, sensors and actuators

  • Emerging Devices, TFT CMOS and SOI-based memory cells

  • Organic, Bio/Med devices/technology modeling

  • Microwave, RF device modeling, HV/Power device modeling

  • Nanoscale CMOS devices and circuits

  • Technology R&D, DFY, DFT and IC Designs

  • Foundry/Fabless Interface Strategies


Paper Submission and Review Schedule:

  • First call for papers:    April 2017

  • Second announcement:    June 2017

  • Special Issue Due:    Dec. 2017


IJHSES Editor-in-Chief

Co-Editors-in-Chiefs

Guest Editors

Michael Shur

Rensselaer Polytechnic Institute (USA)


Wladek Grabinski

MOS-AK Association (EU)

Benjamin Iñiguez

DEEEA, ETSE, URV (SP)

Jean-Michel Sallese

EPFL Lausanne (CH)

Daniel Tomaszewski

ITE Warsaw (PL)


WG250417

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Monday, 24 April 2017

[mos-ak] [2nd Announcement and Call for Papers] 2nd Sino MOS-AK Workshop in Hangzhou (CN) June 29-30, 2017

2nd Sino MOS-AK Workshop  
  in Hangzhou (CN) June 29-30, 2017
     2nd Announcement and Call for Papers   
 
Together with Prof. LingLing Sun, HangZhou Dianzi University, the honorary MOS-AK workshop chair,  Dr. Min Zhang, XMOD (Shanghai), local workshop coordinator and International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the 2nd Sino MOS-AK Workshop which will be held at 会议场所:杭州电子科技大学科技馆 Hangzhou Dianzi University Science & Technology Museum on June 29-20, 2017 in Hangzhou (CN).

Planned MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Important Dates:
  • Preannouncement - March 2016
  • Call for Papers - April 24 2017
  • Final Workshop Program - June. 2017
  • MOS-AK Workshop - June 29-30, 2017
Venue:
会议场所:杭州电子科技大学科技馆
Hangzhou Dianzi University Science & Technology Museum
Hangzhou (CN)
Topics to be covered include the following among other related to the compact/SPICE modeling :
  • Compact Modeling (CM) of the electron devices
  • Advances in semiconductor technologies and processing
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • Open Source TCAD/EDA modeling and simulation
  • CM of passive, active, sensors and actuators
  • Emerging Devices, TFT, CMOS and SOI-based memory cells
  • Microwave, RF device modeling, high voltage device modeling
  • Nanoscale CMOS devices and circuits
  • Technology R&D, DFY, DFT and reliability/ageing IC Designs
  • Foundry/Fabless Interface Strategies
Invited Speakers (tentative list in alphabetic order)
  • Eric Leclerc, UMC Foundry (F)
  • Ling Li, Chinese Academy of Sciences (CN)
  • Helmut Puchner, Cypress Semi (US)
  • Paulius Sakalas, TU Dresden (D)
  • Pete Zampardi, RFMD (US)
  • Thomas Zimmer, Uni. Bordeaux (F)
Online MOS-AK Abstract Submission:
Prospective authors should submit abstract online
Manuscript submission deadline: 29th May 2017 (Monday)
Notification of Acceptance: 5th June 2017 (Monday)
Submission of final manuscript: 19th June 2017 (Monday)
(any related inquiries can be sent to abstrscts@mos-ak.org)

Online Workshop Registration
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

WG240417

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Sunday, 23 April 2017

[mos-ak] [press note] Spring MOS-AK Workshop at DATE Conference in Lausanne, March 31, 2017

 Arbeitskreis Modellierung von Systemen und Parameterextraktion
 Modeling of Systems and Parameter Extraction Working Group
 Spring MOS-AK Workshop at DATE
 Lausanne, March 31, 2017

 The MOS-AK Compact Modeling Association, a global compact/SPICE modeling and Verilog-A standardization forum, held its annual spring workshop as an integral engineering event at the DATE Conference on March 30, 2017 in Lausanne (CH). The event was coorganized by Jean-Michel Sallese, EPFL and its technical program was coordinated by Larry Nagel, OEC (USA) and Andrei Vladimirescu, UCB (USA); ISEP (FR) representing the International MOS-AK Board of R&D Advisers. The workshop was co-sponsored by MPI Corporation (lead sponsor) and Swiss IEEE Section, with technical program promotion provided by the IEEE WiE Group (CH), Eurotraining and NEEDS of nanoHUB.org as well as FOSSEE fossee.in

 

A group of the international academic researchers and modeling engineers attended 12 technical compact modeling presentations covering full development chain form the nanoscaled technologies thru semiconductor devices modeling to advanced IC design support. The MOS-AK speakers have shared their latest perspectives on compact/SPICE modeling and Verilog-A standardization in the dynamically evolving semiconductor industry and academic R&D. 


The event featured advanced technical presentations covering compact model development, implementation, deployment and standardization covering full engineering R&D chain: TCAD/processing, device modeling, transistor level IC design support. These contributions were delivered by leading academic and industrial experts, including: Nicolas Cordero, Tyndall (IE) ASCENT (Nanoelectronics Network) - Open Access to 14nm PDKs; Vadim Kuznetsov, Bauman Moscow TU (RU) The first stable release of Qucs-S and advances in XSPICE model synthesis; Anurag Mangla, ams AG (A) Interactive tool for quick calculation of design oriented MOSFET parameters; Maria-Alexandra Paun, EPFL (CH) Optimal geometry selection for Hall sensors integrated in CMOS technological process; Heinz-Olaf Müller, Plastic Logic (D) Verilog-A model for ferroelectrics in organic electronics; Andrej Rumiantsev, MPI Corp. (TW) New Approach to Reduce Time-to-data when Characterizing Advanced Semiconductor Devices; Mathieu Luisier, ETH Zurich (CH), Physics-based Modeling of Nano-Devices: Requirements and Examples; Felix Salfelder, University of Leeds (UK) Semiconductor Device Compact Modelling with Ageing Effects; Theodor Hillebrand, University of Bremen (D) Unified charge-based Transistor Model including Degradation Mechanisms; Catherine Dehollain, EPFL (CH) Design trade-off between remote power and data communication for remotely powered sensor networks; Sandro Carrara, EPFL (CH) Bio/Nano/CMOS interfaces for Ultrasensitive Memristive Biosensors; Matthias Bucher; TUC (GR), giving an EKV3 model update. The presentations are available online for download at <http://www.mos-ak.org/lausanne_2017>. Selected best presentation will be recommended for further publication in the IJHSES.

 

The MOS-AK Modeling Working Group has various deliverables and initiatives including a book entitled "Open Source CAD Tools for Compact Modeling" and an open Verilog-A directory with models and supporting CAD software. The MOS-AK Association plans to continue its standardization efforts by organizing additional compact modeling meetings, workshops and courses in Europe, USA, India and China throughout 2017/2018 including:


* 2nd Sino MOS-AK Workshop in Hangzhou (June 29-30, 2017)

* 15th MOS-AK ESSDERC/ESSCIRC Workshop in Leuven (Sept.11, 2017)

* 10th International MOS-AK Workshop in Silicon Valley; Dec. 2017

* Spring MOS-AK Workshop Strasbourg (F) March 2018

 

About MOS-AK Association:

MOS-AK, an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common language among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools for the compact models development, validation/implementation and distribution. For more information please visit: mos-ak.org


About MPI Corporation:

Founded in 1995 and headquartered in Hsinchu, Taiwan, MPI Corporation is a global technology leader in Semiconductor, Light Emitting Diode (LED), Photo Detectors, Lasers, Materials Research, Aerospace, Automotive, Fiber Optic, Electronic Components and more. MPI's four main business sectors include Probe Card, Photonics Automation, Advanced Semiconductor Test and Thermal Divisions. MPI products range from various advanced probe card technologies, probers, testers, material handlers, inspection and thermal air systems. Many of these products are accompanied by state-of-the-art Calibration and Test &amp; Measurement software suites. The diversification of product portfolio and industries allows a healthy environment for employee growth and retention. Cross pollination of product technologies allows each new innovation to provide differentiation in areas that are meaningful to our precious customer base. For more information please visit: mpi-corporation.com
WG230417

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Wednesday, 19 April 2017

2017 National Academy of Inventors Fellow Induction

National Academy of Inventors Fellow Induction
Chenming Hu
TSMC Distinguished Professor Emeritus at UC Berkeley


Among all NAI Fellows there are now 94 presidents and senior leaders of research universities and non-profit research institutes, 382 members of the National Academies of Sciences, Engineering, and Medicine, 31 inductees of the National Inventors Hall of Fame, 45 recipients of the U.S. National Medal of Technology and Innovation and U.S. National Medal of Science, 28 Nobel Laureates, 216 AAAS Fellows, 126 IEEE Fellows, and 116 Fellows of the American Academy of Arts & Sciences, among other awards and distinctions. [read more...]

Tuesday, 18 April 2017

2017 IEEE Andrew S. Grove Award

Prof. Sorin Cristoloveanu,  CNRS at IMEP-LAHC
2017 IEEE Andrew S. Grove Award Recipient
“For contributions to silicon-on-insulator technology and thin body devices”

A visionary device physics researcher, Sorin Cristoloveanu saw the potential that silicon-on-insulator (SOI) technology held for the semiconductor industry in producing competitive microelectronics components with improved performance when others considered it a niche field. As early as 1976, he discovered key mechanisms of thin-body devices that have led to the development of transistors from the simplest (zero gate) to the most complicated (four gates). Among several concepts unveiled by his group, the demonstration during the 1980s that volume inversion occurs in all nano-body devices was revolutionary at the time and helped drive research that led to double-gate transistors and today’s tri-gate FinFET devices. His Pseudo-MOSFET method developed in 1992 has become an industry standard for wafer monitoring without having to actually fabricate devices. More recently, Cristoloveanu’s SOI expertise has led to innovative devices for low-power memory and sharp-switching circuits. An IEEE Fellow, Cristoloveanu is the director of research at CNRS at IMEP-LAHC, Grenoble, France [read more...]

Monday, 17 April 2017

[paper] Artificial neural network design for compact modeling of generic transistors

Artificial neural network design for compact modeling of generic transistors
(J Comput Electron; pp. 1-8;  2017)
Lining Zhang and Mansun Chan
Department of ECE, Hong Kong University of Science and
Technology, Kowloon, Hong Kong

Abstract: A methodology to develop artificial neural network (ANN) models to quickly incorporate the characteristics of emerging devices for circuit simulation is described in this work. To improve the model accuracy, a current and voltage data preprocessing scheme is proposed to derive a minimum dataset to train the ANN model with sufficient accuracy. To select a proper network size, four guidelines are developed from the principles of two-layer network. With that, a reference ANN size is proposed as a generic three-terminal transistor model. The ANN model formulated using the proposed approach has been verified by physical device data. Both the device and circuit-level tests show that the ANN model can reproduce and predict various device and circuits with high accuracy [read more...]

(Published online April 9, 2017 http://dx.doi.org/10.1007/s10825-017-0984-9)

Tuesday, 4 April 2017

Starting Framework of the IRDS Roadmap

IEEE has announced the next milestone phase in the development of the International Roadmap for Devices and Systems (IRDS), an IEEE Standards Association (IEEE-SA) Industry Connections (IC) Program sponsored by the IEEE Rebooting Computing (IEEE RC) Initiative with the launch of a series of nine white papers that reinforce the initiative’s core mission and vision for the future of the computing industry. The white papers also identify industry challenges and solutions that guide and support future roadmaps created by IRDS [read more...]

The series of white papers delivers the starting framework of the IRDS roadmap - and through the sponsorship of IEEE RC—will inform the various roadmap teams in the broader task of mapping the devices’ and systems’ ecosystem:
The IRDS leadership team hosted a winter workshop and kick-off meeting at the Georgia Institute of Technology on 1-2 December 2016. Key discoveries from the workshop included the international focus teams’ plans and focus topics for the 2017 roadmap, top-level needs and challenges, and linkages among the teams. Additionally, the IRDS leadership invited presentations from the European and Japanese roadmap initiatives. This resulted in the 2017 IRDS global membership expanding to include team members from the “NanoElectronics Roadmap for Europe: Identification and Dissemination” (NEREID) sponsored by the European Semiconductor Industry Association (ESIA), and the “Systems and Design Roadmap of Japan” (SDRJ) sponsored by the Japan Society of Applied Physics (JSAP).

The IRDS team and its supporters will convene 1-3 April 2017 in Monterey, California, for the Spring IRDS Workshop, which is part of the 2017 IEEE International Reliability Physics Symposium (IRPS). The team will meet again for the Fall IRDS Conference in partnership with the 2017 IEEE International Conference on Rebooting Computing (ICRC) scheduled for 6-7 November 2017 in Washington, D.C. More information on both events can be found here.

IEEE RC is a program of IEEE Future Directions, designed to develop and share educational tools, events, and content for emerging technologies [read more...]