Wednesday, 28 December 2016

FOSS CAD research is in the spotlight

The conference paper "FOSS as an efficient tool for extraction of MOSFET compact model parameters" reached 20 reads at the researchgate.net

FOSS as an efficient tool for extraction of MOSFET compact model parameters
D. Tomaszewski, G. Głuszko, M. Brinson, V. Kuznetsov and W. Grabinski
MIXDES 2016, Lodz, pp. 68-73.


Abstract—A GNU Octave – based application for device-level compact model evaluation and parameter extraction has been developed. The applications main features are as follows: experimental I-V data importing, generating input data for different circuit simulation programs, running the simulation program to calculate I-V characteristics of the specified models, calculating model misfit and its sensitivity to selected parameter variation, and the comparison of experimental and simulated characteristics. Measured I-V data stored by different measurement systems are accepted. Circuit simulations may be done with Ngspice, Qucs and LTSpiceIV. Selected aspects of the application are presented and discussed. 

Tuesday, 27 December 2016

Ken Shirriff Takes Us Inside the IC, For Fun https://t.co/QScTdhgFXV #papers


from Twitter https://twitter.com/wladek60

December 27, 2016 at 09:24PM
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J-EDS Comes of Age https://t.co/4HNl9cQhzh #papers


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December 27, 2016 at 01:07PM
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Sunday, 25 December 2016

Special Issue of Solid-State Electronics, dedicated to EUROSOI-ULIS 2016 https://t.co/fFD9GehZEP #papers #feedly


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December 25, 2016 at 09:14PM
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Tuesday, 20 December 2016

[paper] Analysis and Compact Modeling of Negative Capacitance Transistor

Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current
and Negative Output Differential Resistance
Part II: Model Validation
Girish Pahwa, Student Member, IEEE, Tapas Dutta, Member, IEEE, Amit Agarwal,
Sourabh Khandelwal, Member, IEEE, Sayeef Salahuddin, SM IEEE,
Chenming Hu, IEEE Fellow, and Yogesh Singh Chauhan, SM IEEE 
in IEEE Transactions on Electron Devices, vol. 63, no. 12, pp. 4986-4992, Dec. 2016

doi: 10.1109/TED.2016.2614436

Abstract: In this paper, we show a validation of our compact model for negative capacitance FET (NCFET) presented in Part I. The model is thoroughly validated with the TCAD simulations with respect to ferroelectric thickness scaling and temperature effects. Interestingly, we find that an NCFET with PZT ferroelectric of a large thickness provides a negative output differential resistance in addition to an expected high ON current and a sub-60 mV/decade subthreshold swing. The model is also tested for the Gummel symmetry and its transient capabilities are highlighted through a ring oscillator circuit simulation.

[read more at IEEE Xplore]

Monday, 19 December 2016

[Call for Papers] ESSCIRC–ESSDERC 2017



September 11-14, 2017
LEUVEN - Belgium
www.esscirc-essderc2017.org

ESSCIRC–ESSDERC annual Conference is the most important European forum for the presentation and discussion of recent advances in solid-state devices and circuits: MAKE SURE TO BE PART OF IT!


LOCAL SCIENTIFIC SECRETARIAT
​Cor Claeys (imec, BE) | General Chair
Chantal Deboes (imec, BE) | ESSDERC Chair
Danielle Vermetten (KU Leuven, BE) | ESSCIRC Chair

ORGANIZERS   

TECHNICAL CO-SPONSORSHIP
ESSDERC FINANCIAL SPONSOR 
ESSCIRC FINANCIAL SPONSOR 
DIAMOND SPONSOR  

ORGANIZING SECRETARIAT: Sistema Congressi s.r.l. 










Friday, 16 December 2016

[online] Verilog-AMS Quick Reference and Tutorials

Verilog-AMS is a hardware description language that can model both analog and digital systems. The official description of the Verilog-AMS language is contained in the Verilog-AMS Language Reference Manual.

This site is designed to be your quick reference guide for Verilog-A and Verilog-AMS. The reference material is not complete at this point, but is still quite usable. Over time the reference material should fill out and be supplemented with useful application notes and annotated models that will help you learn to use Verilog-A/MS more effectively. The emphasis is very much on analog and mixed-signal modeling. If you are looking for information on synthesis or the obscure corners of the Verilog language, you must look elsewhere
Both Ken & Henry at Designer’s Guide Consulting aim to make www.VerilogAMS.com your everyday source for information on Verilog-A/MS. Please take a look around, and tell your friends and co-workers. If you have questions about Verilog-AMS, feel free to ask them on
the forum at designers-guide.org.

Wednesday, 14 December 2016

QUCS mentioned in IEEE-EDL paper

Jacopo Iannacci, Fondazione Bruno Kessler (FBK), Trento, Italy, has recently published an article in the IEEE Electron Device Letters (EDL) where he used and explicitly mentioned the QUCS, FOSS CAD/EDA simulator:

RF-MEMS Technology for Future Mobile and High-Frequency Applications:
Reconfigurable 8-Bit Power Attenuator Tested up to 110 GHz
J. Iannacci, M. Huhn, C. Tschoban and H. Pötter
in IEEE EDL, vol. 37, no. 12, pp. 1646-1649, Dec. 2016.

Abstract: In this letter, we present and test—to the best of our knowledge, for the first time—, an 8-bit (256-state) reconfigurable RF-MEMS attenuator, from 10 MHz up to 110 GHz, realized in the CMM-FBK technology. Resistive loads, in series and shunt configuration, are selectively inserted on the RF line by means of electrostatic MEMS ohmic switches. The network exhibits several attenuation levels in the range of −10/−45 dB that are rather flat up to 50 GHz, and a certain number of configurations with VSWR smaller than 4 from nearly dc up to 110 GHz, and better than 2 on a frequency span of ~80 GHz.

doi: 10.1109/LED.2016.2623328

[read more: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7726036&isnumber=7739309]


Top #opensource #conference picks for #2017 https://t.co/nJzg2bSbpq #papers


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December 14, 2016 at 10:37AM
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Tuesday, 13 December 2016

[paper] A surface potential large signal model for AlGaN/GaN HEMTs

A surface potential large signal model for AlGaN/GaN HEMTs
Q. Wu, Y. Xu, Z. Wen, Y. Wang and R. Xu
2016 11th EuMIC, London, UK, 2016, pp. 349-352

doi: 10.1109/EuMIC.2016.7777562

Abstract: This paper presents an accurate analytical surface-potential-based compact model for AlGaN/GaN HEMTs for SPICE-like circuit simulation. Considering the important energy level E0, an easy-implemented analytical continuous expression for the fermi level position Ef was deduced to obtain the surface potential (SP) φs. Then analytical core models for intrinsic charge and drain current are derived based on φs. The model has been implemented in Agilent ADS by using symbolic defined device. Excellent agreement of DC I-V, fundamental output power, power added efficiency and gain is obtained for the first time compared with measurement results. Moreover, the effect of physical parameter such as the barrier thickness d on device characteristic is researched on the basic of this model. The results show that the proposed physical based model can be useful for technological parameters analysis and optimization of process.

[read more: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7777562&isnumber=7777458]

Monday, 12 December 2016

Writing a science/tech book, is it that hard?

Writing a science/tech book, is it that hard?


As a microwave engineer Errikos Lourandakis, PhD, a senior R&D engineer at Helic Inc., started with RF device characterization while working on his PhD. He got fascinated about it and gradually devoted much of his time in the lab (see his lab pic below), though RF and Microwave Measurements were just a vehicle for microwave circuit design that was his actual PhD topic. After 10+ years in academia and industry, recently he has also published his new book "On-Wafer Microwave Measurements and De-embedding"

Errikos' RF and mm-Wave Measurement Lab
Is it worth it? [read more...]

[Fellowship] Physics Based Modeling Simulation and Electrical Characterization

Physics Based Modeling Simulation and Electrical Characterization 
of Quantum Effects in Multigate MOSFETs
[DRDO Fellowship]

Dr. Vimala Palanichamy is looking for Junior Research Fellowship (INR 25000 Stipend per Month) for this project funded by Defense Research and Development Organization (DRDO), Government of India. Please refer below advertisement for applying for Junior Research Fellowship for working on the project: