Monday, 29 April 2013

[mos-ak] [press note] Spring MOS-AK/GSA Workshop in Munich; April 11-12, 2013

press note highlighting recent Spring MOS-AK/GSA Workshop in Munich is available online:
http://www.gsaglobal.org/2013/04/mos-akgsa-munich-workshop-press-note/

The MOS-AK/GSA Modeling Working Group is coordinating several upcoming modeling events: a special compact modeling session at the MIXDES Conference in Gdynia (https://www.mixdes.org); an autumn Q3/2013 MOS-AK/GSA workshop in Bucharest (http://www.mos-ak.org/bucharest/), a winter Q4/2013 MOS-AK/GSA meeting in Washington DC, and a spring Q2/2014 MOS-AK/GSA meeting in London (http://www.mos-ak.org).

Harrison Beasley
Technical Working Groups Manager
Global Semiconductor Alliance (GSA)


--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at http://groups.google.com/group/mos-ak?hl=en.
For more options, visit https://groups.google.com/groups/opt_out.

Friday, 26 April 2013

[mos-ak] BSIM6.0 is industry standard model

recently, Prof. Yogesh Singh Chauhan, the BSIM6 project coordinator and lead developer, has announced that the BSIM6.0 has been approved as industry standard bulk MOSFET model by CMC on April 18, 2013. The BSIM6 model Verilog-A code, its manual and related documents will be available thru its website.

Related links:
BSIM6 Model Home Page
BSIM-EPFL Collaboration Announcement

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at http://groups.google.com/group/mos-ak?hl=en.
For more options, visit https://groups.google.com/groups/opt_out.
 
 

[mos-ak] [on-line publications] Spring MOS-AK/GSA Workshop in Munich; April 11-12, 2013

Together with the workshop host, Prof. Dr. Doris Schmitt-Landsiedel, Lehrstuhl fur Technische Elektronik, TUM and Extended MOS-AK/GSA TPC Committee and the workshop sponsors MunEDA and Tanner EDA as well as the IEEE EDS Chapter Germany, the technical program cosponsor, we have organized recent spring MOS-AK/GSA Workshop in Munich. The workshop's presentations are available on-line at <http://www.mos-ak.org/munich_2013/

The MOS-AK/GSA Modeling Working Group coordinates several upcoming modeling events: a special compact modeling session at the MIXDES Conference in Gdynia (PL) (https://www.mixdes.org);  an autumn Q3/2013 MOS-AK/GSA workshop in Bucharest (RO) (http://www.mos-ak.org/bucharest/), a winter Q4/2013 MOS-AK/GSA meeting in Washington DC, USA, spring Q2/2014 MOS-AK/GSA meeting in London (http://www.mos-ak.org).

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at http://groups.google.com/group/mos-ak?hl=en.
For more options, visit https://groups.google.com/groups/opt_out.
 
 

Wednesday, 24 April 2013

TED Call for Papers on Compact Modeling of Emerging Devices

Compact Models (CMs) for circuit simulation have been at the heart of CAD tools for circuit design for almost five decades. As the mainstream CMOS technology is scaled into the nanometer regime, development of a truly physical and predictive CM for circuit simulation that covers geometry, bias, temperature, DC, AC, RF, and noise characteristics becomes a major challenge. The last call for a special issue on “advanced compact models and 45-nm modeling challenges” was in 2005. Seven years have passed, new technology nodes have been implemented, compact models have evolved and new compact models as well as compact models for new devices are being developed. Therefore, there is a need for another special issue dedicated to the advancement and challenges in core field-effect transistor (FET) models for 32-nm technologies and beyond as well as emerging technologies. For the core FET models, the associated noise/mismatch and reliability/variability models as well as proximity effects have become an essential part of the modeling effort. High-frequency, high-voltage, high-power, high-temperature devices have been extensively investigated, and their CMs are being reported in the literature. Device/circuit interaction and layout-dependent proximity effects are also hot topics today that are essential in nanometer chip designs. It is timely to report advances in these CMs in the 32-nm/22-nm technology era.

Concurrently, nonclassical MOSFETs as well as their CMs, such as multigate FinFETs and nanowire FETs, partially/fully-depleted ultrathin body (UTB) SOT, and thin-film transistors (TFTs), have emerged over the past decades. With the announcement of FinFETs being used in 22-nm and sub-22nm technology nodes, the need for such core models for fabless designers becomes an urgent reality. In these nonclassical devices, transistors are essentially short-channel, narrow-width, and thin-body. Tt is also an interesting topic to discuss and debate on the two different formalisms “top-down” drift-diffusion formulation adding ballistic effects versus “bottom-up” quasi-ballistic formulation adding scattering effects for modeling the real devices that are somewhere in between. Heterogeneous integration of various devices into the CMOS platform also becomes an important trend.
In addition, it is also timely to report advances in CMs of emerging devices beyond traditional silicon CMOS, such as different materials (III-V/Ge channel, organic) and different source/drain injection mechanisms (Schottky-barrier, tunneling, and junctionless FETs). These emerging device options for future VLSI building blocks have been studied extensively, while good physical CMs are still lacking. The special issue in these topics will stimulate research and development to promote modeling efforts such that theory would lead and guide technology realization and selection for future generations.
The special issue for the TRANSACTIONS ON ELECTRON DEVICES on compact modeling of emerging devices is devoted to the review and report of advancements in CMs for 32-nm technologies and beyond, including bulk and nonclassical CMOS and their associated noise/mismatch and reliability/variability models, as well as various emerging devices as future generation device options. It is timely as the industry is in the transition from traditional planar bulk-CMOS towards vertical FinFET technologies, and exploration of heterogeneous integration with various materials and structural choices.


Please submit manuscripts by using the following URL: http://mc.manuscriptcentral.com/ted
MAKE SURE TO MENTION THE SPECIAL ISSUE IN THE COVER LETTER

Paper submission Deadline: June 30, 2013
Scheduled Publication Date: February 2014

Guest Editors:
Xing Zhou, Nanyang Technological University, 
Jamal Deen, McMaster University, 
Benjamin Iniguez, Universitat Rovira i Virgili, 
Christian Enz, Swiss Federal Institute of Technology, 
Rafael Rios, Intel Corp.

If you have any questions about submitting a manuscript, please contact:
IEEE EDS Publications Office
445 Hoes Lane Piscataway JN 08854
Phone: +1 732 562 6855

Digital Object Identifier 10.1109/TED.2013.2253418

Thursday, 11 April 2013

A single European semiconductor strategy is on its way...

From Solid-State Technology:

At the International Semiconductor Strategy Symposium (ISS Europe), the European semiconductor industry affirmed its ability to innovate. More than 170 top industry representatives agreed on a number of joint steps and strategic measures to strengthen their competitiveness and sustainability. The controversial question whether the best way to attack future challenges will be "More Moore" or "More than Moore," ended in an expected compromise, namely that the industry should pursuit both strategies concurrently, the participants of a panel expressed. Whilst the More than Moore sector is traditionally strong in Europe, going on with More Moore is important for two to three device makers in Europe and in particular for the European equipment suppliers which export 80% of their products.
In a global scale, the semiconductor industry is approaching the move to 450mm wafer processing technology – a step that promises to greatly boost the productivity of semiconductor manufacturers. However, since the investment to build a 450mm fab easily exceeds the 10 billion dollar mark, this move is regarded as risky and, for this reason, reserved to only the very largest enterprises. In the past, this perspective divided the European industry into two camps - the "More Moore" group that advocates taking on the 450mm challenge, and the "More than Moore" group which shunned this risky investment and preferred to rely on application-oriented differentiation instead.
At the event SEMI Europe, an industry association embracing enterprises that represent the entire value chain and organizer of the ISS Europe, set up a high-ranking panel discussion on options and choices of a single European semiconductor strategy. The panel proved that entrepreneurial spirit is well alive among Europe's chipmakers, technology suppliers and researchers.

Read more...

Friday, 5 April 2013

[mos-ak] CMC GaN HEMT Model Standardization Effort - Call for Candidate Models

Since its inception, the Compact Model Council (CMC) has collaborated to develop, maintain, and standardize compact models for widely used semiconductor components. CMC members have decided that gallium nitride (GaN) technology is important for their business and the CMC intends to develop its first standard GaN HEMT transistor model. More information about the CMC can be found in the attached document. The ability for the model to generalize from GaN to other III-V FETs would be a bonus but is not a requirement. After the CMC evaluates and standardizes a model for GaN HEMTs, the CMC may decide to extend this effort to all III-V FET/HEMT devices. We are currently soliciting candidate models for this standard.

 

GaN transistors are high electron mobility transistors (HEMTs), a FET technology based on a heterojunction channel and a Schottky / Insulated / Junction (pGaN) gate. The primary applications for GaN transistors are for high voltage / high power devices to be used as for example as switches; and for high frequency / high power devices to be used for example in RF power amplifiers.

 

The CMC plans a three-phase process for identification and evaluation of candidate models. We currently have started Phase I which is a solicitation of available models which meet the fundamental requirements set forth in the attached Requirements Document. The GaN Subcommittee will review written proposals and request top candidates to present an overview of their model at a CMC Meeting. Candidates identified in Phase I which have sufficient support from CMC sponsors will be subjected to thorough testing in subsequent Phases. All developers submitting a proposed standard to CMC for adoption will read and accept the CMC Standard Model Copyright Policy.

 

The attached document lists the model requirements and various types of measurements that the model must reproduce. They include IV curves over various bias and temperature conditions, high frequency measurements, switching measurements, and time dependent measurements to characterize trapping effects. The attached check-list should be used to identify which requirements are or will be met by the candidate model.

 

After a set of candidate models is obtained, Phase II starts with a set of measured data against which the models will be evaluated. This technology has not yet been decided. At this point the CMC will need brief documentation outlining the list of measurements and the data. The details of how the GaN devices are being fabricated, nor the details of their internal structure, will be required. A minimum set of device physical dimensions would be needed in order to feed candidate models with meaningful parameters, such as channel length, channel width, gate to source/drain contact distance, etc. The CMC GaN FET subcommittee will review the proposed measurement data and will determine which data set(s) will be used for model evaluation. It is possible that data from more than one source will be retained for the model evaluation, to cover an as wide as possible range of applications.

 

If you are aware of any organization willing to contribute, please forward this document, or contact the GaN FET subcommittee chair, Samuel Mertens (samuel_mertens(at)agilent.com). Don't hesitate to ask me any questions about the standardization process or the CMC.




--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at http://groups.google.com/group/mos-ak?hl=en.
For more options, visit https://groups.google.com/groups/opt_out.
 
 

Wednesday, 3 April 2013

[mos-ak] [Final Program] Spring MOS-AK/GSA Workshop in Munich; April 11-12, 2013

Together with the workshop host, Prof. Dr. Doris Schmitt-Landsiedel, Lehrstuhl fur Technische Elektronik, TUM and Extended MOS-AK/GSA TPC Committee and the workshop sponsors MunEDA and Tanner EDA as well as the IEEE EDS Chapter Germany, the technical program cosponsor, we have pleasure to invite to the spring MOS-AK/GSA Workshop in Munich 

Venue:
Lehrstuhl fur Technische Elektronik
Room: 5325, 5th floor <http://www.lte.ei.tum.de/index.html>
Technische Universitat Munchen 
Arcisstr. 21 D-80333 Munchen

MOS-AK/GSA Workshop Agenda

April 11 Thursday, Afternoon Session 
13:00 - 16:00
 Oral presentations

Welcome and Workshop Opening
Wladek Grabinski; MOS-AK

Statistical modeling with backward propagation of variance (BPV) and covariance equations
Klaus-Willi Pieper and Elmar Gondro; Infineon Technologies

Circuit Sizing: Corner Models Challenges & Applications
Matthias Sylvester; MunEDA (D)

Compact Modeling Activities in The Framework of the EU-Funded "COMON" Project
Benjamin IƱiguez; URV, Tarragona (SP)

Effective Device Modeling And Verification Tools
Ingo Nickeleit; Agilent Technologies
16:00 - 17:00
 Software/Hardware Demos

MunEDA Framework Applications
Tanner TSpice Verilog-A
Agilent B1505A Power Device Analyzer / Curve Tracer

Networking Evening Event
April 12 Friday, Sessions
9:00 - 12:00
 Morning Oral Presentations

Institute for Technical Electronics (LTE) Presentation 
Prof. Dr. rer. nat. Doris Schmitt-Landsiedel, LTE, TUM (D)

STEEPER: Tunnel Field Effect Transistors (TFETs) Technology, Devices and Applications 
Thomas Schulz and Reinhard Mahnkopf, Intel, IMC, (D)

Current and Future Challenges for TCAD
Christoph Jungemann and Christoph Zimmermann; RWTH Aachen University (D)

Advances in Verilog-A Compact Semiconductor Device Modeling with Qucs/QucsStudio
Mike Brinson; London Metropolitan University, London, UK
12:00 - 13:00
 Lunch
13:00 - 16:00 Afternoon Oral Presentations

FDSOI Devices Bentchmarking
Bich-Yen Nguyen; SOITEC (F)

COMON: SOI Multigate Devices Modeling
Alexander Kloes; THM (D)

COMON: FinFET Modeling Activities 
Udit Monga; Intel, IMC, (D)

COMON: HV MOS Devices Modeling
Matthias Bucher; TUC, (GR)
 End of the Workshop

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at http://groups.google.com/group/mos-ak?hl=en.
For more options, visit https://groups.google.com/groups/opt_out.
 
 

Call for IJNM Papers: Modeling of high-frequency silicon transistors

Silicon transistors (STs) have been the workhorse of the electronics industry ever since its inception. Although STs historically have been used primarily in digital and low-frequency analog applications, they increasingly are being adopted for high-frequency analog purposes as well. This trend is fueled by the introduction of new fabrication methods, novel materials, and transistor architectures that permit aggressive downscaling into the nanometer regime. Along these lines, considerable attention currently is being devoted to the FinFET, which is an innovative multiple-gate field effect transistor offering the important advantage of being compatible with conventional planar CMOS technology.

Modeling and simulation are indispensable in the development of high-frequency STs. Indeed, ST models and simulations provide indispensable feedback for improving device fabrication processes and serve as a valuable tool for optimizing circuit designs. Unfortunately, the predictive power of modeling and simulation techniques for STs for digital and low-frequency applications oftentimes diminishes when applied to high-frequency analog STs. For modeling and simulation methods to drive the development of high-frequency ST technology, they must adapt as well. 

The purpose of this Special Issue is to publish high-quality contributions addressing the modeling and simulation of high-frequency STs. A wide range of topics will be covered, ranging from bipolar to ?eld effect transistors and from linear to noise and non-linear models. Although the main focus of the Special Issue will be the extraction of high-frequency models, papers addressing other aspects of ST modeling will be considered as well. This issue will contain both invited and contributed papers. Manuscripts for this Special Issue should adhere to the requirements for regular papers of the IJNM as specified in the Author Guidelines at http://onlinelibrary.wiley.com/journal/10.1002/ (ISSN)1099-1204/homepage/ForAuthors.html.

Potential contributors may contact the Guest Editors to determine the suitability of their contribution to the Special Issue. All manuscripts should be submitted via the IJNM’s manuscript website http://mc.manuscriptcentral.com/ijnm, with a statement that they are intended for this Special Issue.

Guest Editors:
Manuscript submission deadline: April 30, 2013