Monday, 29 October 2012

[mos-ak] [2nd announcement] 5th International MOS-AK/GSA Workshop in San Francisco, Dec. 12, 2012

Together with the Organizing Committee and Extended MOS-AK/GSA TPC Committee, we have pleasure to invite to the 5th International MOS-AK/GSA Workshop in San Francisco, Dec. 12, 2012 http://www.mos-ak.org/sanfrancisco_2012/ The event will be organized in timeframe of the IEDM and CMC meetings.

Venue:
730 Montgomery Street
San Francisco, CA 94111, USA

Important Dates:

R&D Topics to be covered include the following:
  • Advances in semiconductor technologies and processing
  • Compact Modeling (CM) of the electron devices
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • CM of passive, active, sensors and actuators
  • Emerging Devices, CMOS and SOI-based memory cells
  • Microwave, RF device modeling, high voltage device modeling
  • Nanoscale CMOS devices and circuits
  • Technology R&D, DFY, DFT and IC Designs
  • Foundry/Fabless Interface Strategies

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Monday, 22 October 2012

[mos-ak] [Call for Papers] 10th International Workshop on Compact Modeling

10th International Workshop on Compact Modeling (IWCM 2013)
January 22 (Tuesday), 2013; Pacifico Yokohama, Yokohama, Japan

Scope:
The workshop provides an opportunity for the discussion and the presentation of advances in modeling and simulation of nano-scale devices and circuits.
Topics:
  • Compact modeling for all kinds of devices
  • Parameter extraction methodology and strategy
  • Circuit simulation techniques and methods
Abstract Submission:
Authors are requested to prepare a camera-ready abstract with a minimum 2 and maximum 8 pages including figures for  publication in the workshop proceedings. The electronic file of the paper should be submitted in PDF or MS-Word format to hjm@hiroshima-u.ac.jp.  IWCM 2013 is held co-located with ASP-DAC 2013 and paper templates in LaTex and Word formats are downloadable from the ASP-DAC 2013 website. Deadline for abstract submission is November 30th, 2012.

Organization Committee:
Chair: H. J. Mattausch (Hiroshima University, Japan)
Co-Chair: M. Chan (Hong Kong University of Science & Technology, H.K.)
Committee Members: 
Y. Cao (Arizona State University, USA)
W. Grabinski (EPFL, Switzerland)
J. He (Peking University, China)
J. J. Liou (University of Central Florida, USA)
T. Nakagawa (AIST, Japan)
D. Navarro (Silvaco, Japan)
M. Miura-Mattausch (Hiroshima University, Japan)
Y. J. Park (Seoul National University, Korea)
Z. Yu (Tsinghua University, China)
Contact:
If you have any question, please contact hjm@hiroshima-u.ac.jp.
Registration is free, but Yen 2000 are requested for the proceedings.

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Friday, 5 October 2012

QucsStudio 1.4.2

A new version of QucsStudio has just been released for general use. The latest version is mainly  bug fixes but does contain a number of new/improved features. A list of the changes are given below:

  • some corrections in help system
  • component names in noise contribution analysis with subcircuit prefix
  • reduced time step warnings in transient analysis
  • bugfix: differential voltages in equations
  • in equations: allow suffix in node names
  • bugfix: directory MinGW\mingw32\bin\ exists again
  • bugfix: crash in diagram dialog if clicking on empty variable area
  • new component: photodiode
  • new equation function: stoa()
  • bugfix: spaces allowed between function name and "("
  • added InP permittivity in property list
  • bugfix: correct text in C++ symbol string
  • error message for wrong index in equation variables

This is likely to be one of the last releases in the QucsStudio 1.4 series.  Work has started on QucsStudio series 2.0.0.  QucsStudio 2.0.0 is expected to offer users significant improvements in simulation and modelling capabilities.  The first of the new releases will coincide with the tenth anniversary of the first release of Qucs next year.

QucsStudio can be downloaded from the QucsStudio homepage at http://www.mydarc.de/DD6UM/QucsStudio/qucsstudio.html

Contact: Mike Brinson

[mos-ak] MOS-AK/GSA Bordeaux workshop press release

MOS-AK/GSA Modeling Working Group Holds Summer Workshop in Bordeaux

Experts Share Insight on Compact Device Modeling with Emphasis on Simulation-Aware Models
http://www.gsaglobal.org/2012/10/mos-akgsa-modeling-working-group-holds-summer-workshop-in-bordeaux/

SAN JOSE, Calif. (October 1, 2012) – The MOS-AK/GSA Modeling Working Group, a global compact modeling standardization forum, has delivered their 10th compact modeling workshop, presented on Sept. 21, 2012 as an integral part of the ESSDERC/ESSCIRC Conference in Bordeaux (F). The event was organized receiving full sponsorship provided by the leading industrial partners including Agilent Technologies (USA), LFoundry (D), CSEM (CH), STMicroelectronics (F), and AMS (A). The French Branch of IEEE EDS, FP7 COMON Project, Eurotraining and MOSIS Services were among the workshop technical program promoters. More than 50 international academic researchers and modeling engineers attended three sessions to hear 16 technical compact modeling talks and poster presentations. 

The workshop's three sessions focused on the nanowire TFET and organic TFT technologies, advanced compact modeling for analog/RF IC design application, computer-aided design (CAD), EDA simulations highlighting recent developments of Verilog-A compact models and its standardization. The 10th MOS-AK/GSA ESSDERC/ESSCIRC workshop was opened by invited researchers highlighting active women contributions to compact modeling R&D. The speakers discussed: the EKV model for LC-VCO optimization (M. H. Fino, UNL); physics-based analytical model of nanowire TFETs (E. Gnani, Uni. Bologna); analytical models for disordered and polycrystalline organic TFTs (M. Raja, Uni. Liverpool); Hall effect sensors performance assessment using 3D physical simulations (M.-A. Paun, EPFL); and physical compact model of a CBRAM cell (M. Reyboz, CEA/LETI).  

Afterward invited international modeling experts presented: device modeling DC measurements challenges (F. Sischka, Agilent Technologies); surface-potential-based compact model of AlGaN/GaN HEMT power transistors (P. Martin, CEA/LETI); millimeter-wave CMOS device modeling and issues (K. Okada, TITech); measurement and modeling of CMOS devices in short millimeter wave (M. Fujishima, Hiroshima University);  thermal network extraction in ultra-thin-body SOI MOSFETs (Y. S. Chauhan, UC Berkeley); compact modeling of SiC JFET power devices (M. Bucher, TUC Chania); SMASH-ACMI for integration and validation of Verilog-A compact models in a SPICE simulator (G. Depeyrot, Dolphin Integration); parametric yield-oriented IC design based on cumulative distribution function and open-source EDA tools (D. Tomaszewski, ITE); analytical calculation of surface-potential in AlGaAs/GaAs and AlGaN/GaN HEMT devices (S. Khandelwal analytical 2D model for source/drain band-to-band tunneling in silicon double-gate TFETs (M. Graef, THM) gate-level modeling for CMOS circuit simulation with ultimate FinFETs (N. Chevillon, InESS). The session oral and poster presentations are available for download at http://mos-ak.org/bordeaux/

The MOS-AK/GSA Modeling Working Group coordinates several upcoming modeling events: a winter Q4/2012 MOS-AK/GSA meeting in San Francisco, CA, USA, followed by a spring Q2/2013 MOS-AK/GSA meeting in Munich, a special compact modeling session at the MIXDES Conference in Gdynia, Poland (https://www.mixdes.org); and an autumn Q3/2013 MOS-AK/GSA workshop in Bucharest, Romania.

About MOS-AK/GSA Modeling Working Group:

In January 2009, GSA merged its efforts with MOS-AK, a well-known industry compact modeling volunteer group primarily focused in Europe, to re-activate its Modeling Working Group. Its purpose, initiatives and deliverables coincide with MOS-AK's purpose, initiatives and deliverables. The Modeling Working Group plays a central role in developing a common language among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact model standardization and related tools for model development, validation/implementation and distribution.www.gsaglobal.org/working-groups/analog-mixed-signal 

About GSA:

The Global Semiconductor Alliance mission is to accelerate the growth and increase the return on invested capital of the global semiconductor industry by fostering a more effective ecosystem through collaboration, integration and innovation. It addresses the challenges within the supply chain including IP, EDA/design, wafer manufacturing, test and packaging to enable industry-wide solutions. Providing a platform for meaningful global collaboration, the Alliance identifies and articulates market opportunities, encourages and supports entrepreneurship, and provides members with comprehensive and unique market intelligence. Members include companies throughout the supply chain representing 30 countries across the globe.www.gsaglobal.org

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Tuesday, 2 October 2012

[mos-ak] C4P: 5th International MOS-AK/GSA Workshop in San Francisco, Dec. 12, 2012

Together with the Organizing Committee and Extended MOS-AK/GSA TPC Committee, we have pleasure to invite to the 5th International MOS-AK/GSA Workshop in San Francisco, Dec. 12, 2012 http://www.mos-ak.org/sanfrancisco_2012/ The event will be organized in timeframe of the IEDM and CMC meetings.

Venue:
730 Montgomery Street
San Francisco, CA 94111, USA

Important Dates:
  • Call for Papers - Oct. 2012
  • Submission deadline - Nov. 15, 2012
  • Final Workshop Program - Nov. 30 2012
  • MOS-AK/GSA Workshop - Dec. 12, 2012

R&D Topics to be covered include the following:
  • Advances in semiconductor technologies and processing
  • Compact Modeling (CM) of the electron devices
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • CM of passive, active, sensors and actuators
  • Emerging Devices, CMOS and SOI-based memory cells
  • Microwave, RF device modeling, high voltage device modeling
  • Nanoscale CMOS devices and circuits
  • Technology R&D, DFY, DFT and IC Designs
  • Foundry/Fabless Interface Strategies

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[mos-ak] MOS-AK/GSA Bordeaux workshop on-line publications

The MOS-AK/GSA Modeling Working Group, a global compact modeling standardization forum, has delivered 10th subsequent compact modeling workshop which was organized on Sept. 21, 2012 as an integral part of the ESSDERC/ESSCIRC Conference in Bordeaux (F). The event was organized receiving full organization sponsorship provided by the leading industrial partners including Agilent Technologies (USA), LFoundry (D), CSEM (CH), STMicroelectronics (F), and AMS (A). The French Branch of IEEE EDS, FP7 COMON Project, Eurotraining and MOSIS Services were among the workshop technical program promoters. More than 50 international academic researchers and modeling engineers attended three sessions to hear 16 technical compact modeling talks and poster presentations.

The workshop's three sessions focused on the nanowire TFET and organic TFT technologies, advanced compact modeling for analog/RF IC design application, computer-aided design (CAD), EDA simulations highlighting recent developments of Verilog-A compact models and its standardization. The 10th MOS-AK/GSA ESSDERC/ESSCIRC workshop was opened by fifth invited female researchers highlighting active women contribution to compact modeling R&D. Afterward invited international modeling experts presented their recent modeling work. The session oral and poster presentations are available for download at http://mos-ak.org/bordeaux/

The MOS-AK/GSA Modeling Working Group coordinates several upcoming modeling events: 

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