Friday, 18 May 2012

Intel's FinFETs are less fin and more triangle

EE Times staff -- EDN, May 17, 2012

LONDON -- Reverse engineering and analysis consultancy Chipworks Inc  has posted microscope cross-sections of parts of the 22-nm Ivy Bridge processor from Intel that has revealed that the FinFETs, which Intel calls tri-gate transistors, are in fact trapezoidal, almost triangular, in cross-section.

The ICs were 64-bit, four-core Xeon E3-1230 CPUs intended for the server market, which Chipworks (Ottawa, Ontario) said it obtained in Hong Kong, China.

The triangular section is markedly different to the idealized rectangular section that Intel had shown previously in 2011. However, it is not clear whether the non-vertical sides to the fins are a non-critical manufacturing artifact or are deliberately engineered by Intel and have a critical impact on electron mobility or yield.

Gold Standard Simulations Ltd (or GSS base in Glasgow, Scotland), a spin-off from the University of Glasgow led by Professor Ase Asenov as CEO, responded by saying on its Web site: "There is a lot of speculation about the possible advantages and disadvantages of the trapezoidal, or almost triangular, shaped 'bulk' FinFET." GSS has performed a simulation analysis of the FinFET using its statistical 3-D TCAD simulator called Garand.



Comparison of the TEM image of one of the FinFETs from Figure 6 of the Chipworks blog (linked above) with the Garand simulation domain of Gold Standard Simulations. 

GSS' simulation was used to explore the dependence of threshold voltage on gate length for the trapezoidal Intel transistor and an equivalent rectangular-fin transistor. "Clearly the rectangular fin has better short channel effects. Still, the million-dollar question is if the almost-triangular shape is on-purpose design, or is this, what bulk FinFET technology can achieve in terms of the fin etching?"

The comparisons between dimensionally comparable rectangular and trapezoidal FinFETs are not markedly different but as GSS had no knowledge of doping profiles it assumed a lightly doped channel. At the same time GSS acknowledged that there is a high doping concentration stopper below the fin in the shallow trench isolation (STI) region. "Clearly FinFETs are more complicated devices in terms of understanding and visualization compared to the old bulk MOSFETs," GSS concluded.

This story was originally posted by EE Times.

Thursday, 17 May 2012

[mos-ak] C4P 10th MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Bordeaux, Sept. 21, 2012

C4P 10th MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Bordeaux, Sept. 21, 2012

Together with the Organizing Committee and Extended MOS-AK/GSA TPC Committee, we have pleasure to invite to the 10th MOS-AK/GSA Compact Modeling Workshop at the ESSDERC/ESSCIRC Conference in Bordeaux, Sept. 21, 2012.  

The terms of participation, intending participants and authors should also note the following dates: 
  • Preannouncement - April 2012
  • Call for Papers - May 2012
  • Abstract submission deadline - June 2012
  • Final Workshop Program - July 2012
  • MOS-AK/GSA Workshop - Sept. 21, 2012
Further details and updates: <
Email contact: <

- with regards - WG (for the MOS-AK/GSA Committee
MIXDES Special Modeling Sesion Warsaw (PL) May 24-26, 2012
COMON Tranining Course Tarragona (SP) June 28-19, 2012 
MOS-AK/GSA Bordeaux (F) Sept.21, 2012 
MOS-AK/GSA San Francisco, CA Q4 2012 

You received this message because you are subscribed to the Google Groups "mos-ak" group.
To view this discussion on the web visit
To post to this group, send email to
To unsubscribe from this group, send email to
For more options, visit this group at

Wednesday, 16 May 2012

[mos-ak] MOS-AK/GSA Dresden workshop on-line publications

MOS-AK/GSA Dresden workshop on-line publications are available, visit: 

The MOS-AK/GSA Modeling Working Group, a global compact modeling standardization forum, held its annual spring workshop on April 26-27, 2012 at the Design Automation Division EAS of the Fraunhofer Institute for Integrated Circuits IIS in Dresden, Germany. More than 50 international academic researchers and modeling engineers attended four sessions to hear 16 technical compact modeling talks and poster presentations. The MOS-AK/GSA Modeling Working Group organized the event supported by Joachim Haase Fraunhofer IIS/EAS in Dresden, and a complementary X-FAB clean room visit, poster session and open networking event was hosted by Alexander Petr, X-FAB in Dresden.

As a result of an unfolded compact modeling discussion, the MOS-AK Group followed recommendation of Alexander Petr, X-FAB, a member of the Extended MOS-AK/GSA Compact Modeling Committee, to create a compact modeling open directory (CMOD: The directory will list available SPICE/Compact models including Verilog-A models for an extensive range of the semiconductor devices. The MOS-AK/GSA Group believes that the CMOD initiative will also stimulate further compact model developments for inter domain technologies and multidisciplinary applications.

The MOS-AK/GSA Dresden Press Note can be found here: 
and selected workshop photos are here:

I hope, we would have a next chance to meet us with your academic and industrial partners at future MOS-AK/GSA modeling events (check the list below).

- with regards - WG (for the MOS-AK/GSA Committee
MIXDES Special Modeling Sesion Warsaw (PL) May 24-26, 2012
COMON Tranining Course Tarragona (SP) June 28-19, 2012 
MOS-AK/GSA Bordeaux (F) Sept.21, 2012 
MOS-AK/GSA San Francisco, CA Q4 2012 

You received this message because you are subscribed to the Google Groups "mos-ak" group.
To view this discussion on the web visit
To post to this group, send email to
To unsubscribe from this group, send email to
For more options, visit this group at

Friday, 11 May 2012

Programme of the 2nd Training Course on Compact Modeling

The 2nd Training Course on Compact Modeling (TCCM) will be held in Tarragona (Catalonia, Spain) on June 28-29 2012.
 It will be organized by the NEPHOS Group, of the Department of Electronic, Electrical and Automatic Control Engineering at the Universitat Rovira i Virgili (Tarragona)..
The General Chairman is myself, Prof. Benjamin Iñiguez.

The Training Course on Compact Modeling will consist of l2 lectures addressing relevant topics in the compact modeling of advanced electron devices. These lectures will be conducted by top experts in the field. Most of the lectures will target compact modeling issues applicable to many electron devices. In particular, emphasis will be given on MOSFETs (bulk, SOI, Multi-Gate and High Voltage MOS structures) and HEMTs.
Attendees will  get very useful information on the different aspects of advenced device modelling. This training course is therefore recommended to Master and Ph D students, as well as postdocs and early stage researchers in companies, and not necessarily doing research on modelling.

Here is the final programme of the Training Course on Compact Modeling

 8:30   Training Courses Opening Session
           Benjamin Iniguez (Universitat Rovira i Virgili, Tarragona, Spain)

8:55  "Tunnel and quasi-ballistic transport modelling in nanoscale MOS devices".
         Raphaël Clerc (Institut National Polytechnique de Grenoble, France)

11:15 Coffee break

11:40 "3D analytical modelling techniques for Tri-Gate MOS structures"
            Romain Ritzenthaler (IMEC, Belgium)

12:50 "S-parameter and nonlinear RF modelling"
            Franz Sischka (Agilent Technologies, Böblingen, Germany)

14:00   Lunch
15:15   "Low frequency noise modeling"
            Frédéric Martinez (Université de Montpellier 2, France)

16:25 Quantum confinement models for nanoelectronic devices
          David Jiménez (Universitat Autònoma de Barcelona, Spain)

20:30    Gala dinner

June 29 2012

8:45   "Thermal modelling of RF and microwave devices"
        Giovanni Ghione (Politecnico di Torino, Italy)

9:55  "Statistical modelling techniques"
        Colin C. McAndrew (Freescale Semiconductors, Phoenix, AZ, USA)

11:05  Coffee break

11:30 High frequency noise modeling
          Jamal Deen (McMaster University, Canada)

12:50  "QucsStudio: A second generation Qucs software package for compact semiconductor device model development based on interactive and compiled equation-defined modelling techniques plus circuit simulation"
           Mike Brinson (Metropolitan University of London, UK)

14:00   Lunch

15:15  "Flicker noise measurements and characterization"
           Thomas Gneiting (AdMOS GmbH, Frickenhausen, Germany)

16:25 "World-wide Model Standardization at the CMC, and DRAM Modeling Needs"
            Peter Lee (vice-chair of the Compact Modeling Council, Elpida Memory, Japan)

Look at:

The Training Course on Compact Modeling is an event sponsored by the FP7 “COMON” (COmpact MOdelling Network) IAPP Project (which is coordinated by the Universitat Rovira i Virgili) in collaboration with the IEEE EDS Compact Modeling Technical Committee.

  • Registration will be cheap, in particular before June 16 : and will include lunches, coffee breaks and a Gala Dinner on June 28th.

Monday, 7 May 2012

[book] Lectures on the modeling elements of integrated circuits in microelectronics

Лекции по моделированию элементов интегральных схем микроэлектроники
Игорь Иванович Абрамов
ISBN: 978-3-8484-8201-6
LAP Lambert Academic Publishing (2012-04-11)