Thursday, 20 December 2012

[mos-ak] [on-line publications] 5th International MOS-AK/GSA Workshop in San Francisco, Dec. 12, 2012

The MOS-AK/GSA Working Group, a global compact modeling standardization forum, has delivered their 5th international compact modeling workshop, organized on Dec. 12, 2012 in the time frame of the IEDM Conference in San Francisco. The event was organized at swissnex receiving full sponsorship provided by leaders in electronic design automation including Agilent Technologies and Mentor Graphics. The FP7 COMMON Project, Eurotraining, and MOSIS Services were among the workshop technical program promoters. More than 40 international academic researchers and modeling engineers attended two sessions to hear 11 technical compact modeling talks. The session oral presentations are available for download at http://www.mos-ak.org/sanfrancisco_2012/

The compact modeling panel discussion moderated by Larry Nagel concluded the MOS-AK/GSA workshop. Invited international academic researchers and modeling engineers reviewed the status of compact modeling standardization and agreed that the Verilog-A standard offers a unique platform for compact model developments, validation, exchange and implementation into commercial as well as open source CAD/EDA tools. The panelists also pointed out the needs of further Verilog-A standard extensions and broader Verilog-AMS language definitions to better support compact device modeling, in particular focusing on Analog/RF noise applications. It is also expected that open source developers will actively contribute to standards promotion, addressing the challenges of related CAD/EDA software developments, such as Verilog-AMS debuggers supporting new model validations; and full featured, integral Verilog-AMS simulators for semiconductor device model benchmarking.

The MOS-AK/GSA Modeling Working Group coordinates several upcoming modeling events: a spring Q2/2013 MOS-AK/GSA meeting in Munich (D), followed by a special compact modeling session at the MIXDES Conference in Gdynia (PL); and an autumn Q3/2013 MOS-AK/GSA workshop in Bucharest (RO).

[read also recent press release]

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Wednesday, 5 December 2012

The 20nm Moore's Law Challenge - FinFET versus SOI technology... with John Chen, Nvidia

From Electronics weSRCH:

http://electronics.wesrch.com/weqEL1UYOB

Some say Moore's Law for semiconductors has stopped. But the world of 20nm technology is coming fast.  My guest, John Chen, Vice President, Wafer Foundry Group and Global Operations of Nvidia, was here to talk about it. He talks about the strengths and weaknesses of FinFET and SOI, including the power benefits and the design challenges.  Then we examine the question of Moore's Law slowing, followed up with the need for greater collaboration between fabless and foundry in a way that looks like a Virtual IDM.

The interview is in the original link, and it's quite interesting...

Tuesday, 27 November 2012

[mos-ak] [Final Program] 5th International MOS-AK/GSA Workshop in San Francisco, Dec. 12, 2012

Together with the Organizing Committee and Extended MOS-AK/GSA TPC Committee and the MOS-AK prime sponsors Agilent Technologies and Mentor Graphics, we have pleasure to invite to the 5th International MOS-AK/GSA Workshop in San Francisco, Dec. 12, 2012 http://www.mos-ak.org/sanfrancisco_2012/ The event will be organized in timeframe of the IEDM and CMC meetings.

Venue:
730 Montgomery Street
San Francisco, CA 94111, USA


Workshop Agenda:
  • MOS-AK/GSA Workshop - Dec. 12, 2012 (9:00am - 5:00pm)
    • 9:00am - 12:00 Morning Session
    • 1:00pm - 4:00pm Afternoon Session
    • 4:00pm - 5:00pm Panel: Status and Future of Verilog-A Compact Modeling Standardization
      • Moderator: Larry Nagel
    • 5:00pm End of the MOS-AK/GSA workshop

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Thursday, 15 November 2012

Workshop on Advanced Materials and Devices


The Workshop on Advanced Materials and Devices will be held on March 13 to 15, 2013, at the University of Havana, Cuba. This meeting is a continuation of the“Workshop Espana-Mexico-Brazil”, first organized on March 16 to 18 2011 at CINVESTAV, Mexico. As in its previous issue, the main objective of the Workshop is to discuss the results of research projects done by collaborating groups, as well as to plan future activities of interest to the participants.
The workshop will count with the participation of researchers from different universities of Spain, Mexico, Brazil and Cuba.
As a more general objective, the meeting is interested in including new colleagues from other places. R9 EDS Chapters committee is also interested in promoting Latin American EDS members to join to these activities.
The extended abstracts will be published and distributed at the Workshop.
Please link to the corresponding entry on this page, to download the format for preparing the abstract.
The deadline for abstract presentation is December 24, 2012.
Abstracts should be sent to mestrada@cinvestav.mx
Recommended hotels are Hotel Nacional and Hotel Habana Libre
Special prices for the activity will be posted son.

Other important information will be incorporated to the page as the activity approaches.
Organizing committee:
Rodrigo Picos Universitat del Illes Balears, Spain
Benjamin Iniguez Universitat Rovira I virgili, Spain
Magali Estrada CINVESTAV-IPN, Mexico
Maria Sanchez Universidad de la Habana

Wednesday, 14 November 2012

Visit semiconductorconnect.org



The semiconductorconnect.org aims to help the semiconductor industry connect - jobs with candidates, events with attendees, students with placements. [Read more...]


Monday, 29 October 2012

[mos-ak] [2nd announcement] 5th International MOS-AK/GSA Workshop in San Francisco, Dec. 12, 2012

Together with the Organizing Committee and Extended MOS-AK/GSA TPC Committee, we have pleasure to invite to the 5th International MOS-AK/GSA Workshop in San Francisco, Dec. 12, 2012 http://www.mos-ak.org/sanfrancisco_2012/ The event will be organized in timeframe of the IEDM and CMC meetings.

Venue:
730 Montgomery Street
San Francisco, CA 94111, USA

Important Dates:

R&D Topics to be covered include the following:
  • Advances in semiconductor technologies and processing
  • Compact Modeling (CM) of the electron devices
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • CM of passive, active, sensors and actuators
  • Emerging Devices, CMOS and SOI-based memory cells
  • Microwave, RF device modeling, high voltage device modeling
  • Nanoscale CMOS devices and circuits
  • Technology R&D, DFY, DFT and IC Designs
  • Foundry/Fabless Interface Strategies

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Monday, 22 October 2012

[mos-ak] [Call for Papers] 10th International Workshop on Compact Modeling

10th International Workshop on Compact Modeling (IWCM 2013)
January 22 (Tuesday), 2013; Pacifico Yokohama, Yokohama, Japan

Scope:
The workshop provides an opportunity for the discussion and the presentation of advances in modeling and simulation of nano-scale devices and circuits.
Topics:
  • Compact modeling for all kinds of devices
  • Parameter extraction methodology and strategy
  • Circuit simulation techniques and methods
Abstract Submission:
Authors are requested to prepare a camera-ready abstract with a minimum 2 and maximum 8 pages including figures for  publication in the workshop proceedings. The electronic file of the paper should be submitted in PDF or MS-Word format to hjm@hiroshima-u.ac.jp.  IWCM 2013 is held co-located with ASP-DAC 2013 and paper templates in LaTex and Word formats are downloadable from the ASP-DAC 2013 website. Deadline for abstract submission is November 30th, 2012.

Organization Committee:
Chair: H. J. Mattausch (Hiroshima University, Japan)
Co-Chair: M. Chan (Hong Kong University of Science & Technology, H.K.)
Committee Members: 
Y. Cao (Arizona State University, USA)
W. Grabinski (EPFL, Switzerland)
J. He (Peking University, China)
J. J. Liou (University of Central Florida, USA)
T. Nakagawa (AIST, Japan)
D. Navarro (Silvaco, Japan)
M. Miura-Mattausch (Hiroshima University, Japan)
Y. J. Park (Seoul National University, Korea)
Z. Yu (Tsinghua University, China)
Contact:
If you have any question, please contact hjm@hiroshima-u.ac.jp.
Registration is free, but Yen 2000 are requested for the proceedings.

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Friday, 5 October 2012

QucsStudio 1.4.2

A new version of QucsStudio has just been released for general use. The latest version is mainly  bug fixes but does contain a number of new/improved features. A list of the changes are given below:

  • some corrections in help system
  • component names in noise contribution analysis with subcircuit prefix
  • reduced time step warnings in transient analysis
  • bugfix: differential voltages in equations
  • in equations: allow suffix in node names
  • bugfix: directory MinGW\mingw32\bin\ exists again
  • bugfix: crash in diagram dialog if clicking on empty variable area
  • new component: photodiode
  • new equation function: stoa()
  • bugfix: spaces allowed between function name and "("
  • added InP permittivity in property list
  • bugfix: correct text in C++ symbol string
  • error message for wrong index in equation variables

This is likely to be one of the last releases in the QucsStudio 1.4 series.  Work has started on QucsStudio series 2.0.0.  QucsStudio 2.0.0 is expected to offer users significant improvements in simulation and modelling capabilities.  The first of the new releases will coincide with the tenth anniversary of the first release of Qucs next year.

QucsStudio can be downloaded from the QucsStudio homepage at http://www.mydarc.de/DD6UM/QucsStudio/qucsstudio.html

Contact: Mike Brinson

[mos-ak] MOS-AK/GSA Bordeaux workshop press release

MOS-AK/GSA Modeling Working Group Holds Summer Workshop in Bordeaux

Experts Share Insight on Compact Device Modeling with Emphasis on Simulation-Aware Models
http://www.gsaglobal.org/2012/10/mos-akgsa-modeling-working-group-holds-summer-workshop-in-bordeaux/

SAN JOSE, Calif. (October 1, 2012) – The MOS-AK/GSA Modeling Working Group, a global compact modeling standardization forum, has delivered their 10th compact modeling workshop, presented on Sept. 21, 2012 as an integral part of the ESSDERC/ESSCIRC Conference in Bordeaux (F). The event was organized receiving full sponsorship provided by the leading industrial partners including Agilent Technologies (USA), LFoundry (D), CSEM (CH), STMicroelectronics (F), and AMS (A). The French Branch of IEEE EDS, FP7 COMON Project, Eurotraining and MOSIS Services were among the workshop technical program promoters. More than 50 international academic researchers and modeling engineers attended three sessions to hear 16 technical compact modeling talks and poster presentations. 

The workshop's three sessions focused on the nanowire TFET and organic TFT technologies, advanced compact modeling for analog/RF IC design application, computer-aided design (CAD), EDA simulations highlighting recent developments of Verilog-A compact models and its standardization. The 10th MOS-AK/GSA ESSDERC/ESSCIRC workshop was opened by invited researchers highlighting active women contributions to compact modeling R&D. The speakers discussed: the EKV model for LC-VCO optimization (M. H. Fino, UNL); physics-based analytical model of nanowire TFETs (E. Gnani, Uni. Bologna); analytical models for disordered and polycrystalline organic TFTs (M. Raja, Uni. Liverpool); Hall effect sensors performance assessment using 3D physical simulations (M.-A. Paun, EPFL); and physical compact model of a CBRAM cell (M. Reyboz, CEA/LETI).  

Afterward invited international modeling experts presented: device modeling DC measurements challenges (F. Sischka, Agilent Technologies); surface-potential-based compact model of AlGaN/GaN HEMT power transistors (P. Martin, CEA/LETI); millimeter-wave CMOS device modeling and issues (K. Okada, TITech); measurement and modeling of CMOS devices in short millimeter wave (M. Fujishima, Hiroshima University);  thermal network extraction in ultra-thin-body SOI MOSFETs (Y. S. Chauhan, UC Berkeley); compact modeling of SiC JFET power devices (M. Bucher, TUC Chania); SMASH-ACMI for integration and validation of Verilog-A compact models in a SPICE simulator (G. Depeyrot, Dolphin Integration); parametric yield-oriented IC design based on cumulative distribution function and open-source EDA tools (D. Tomaszewski, ITE); analytical calculation of surface-potential in AlGaAs/GaAs and AlGaN/GaN HEMT devices (S. Khandelwal analytical 2D model for source/drain band-to-band tunneling in silicon double-gate TFETs (M. Graef, THM) gate-level modeling for CMOS circuit simulation with ultimate FinFETs (N. Chevillon, InESS). The session oral and poster presentations are available for download at http://mos-ak.org/bordeaux/

The MOS-AK/GSA Modeling Working Group coordinates several upcoming modeling events: a winter Q4/2012 MOS-AK/GSA meeting in San Francisco, CA, USA, followed by a spring Q2/2013 MOS-AK/GSA meeting in Munich, a special compact modeling session at the MIXDES Conference in Gdynia, Poland (https://www.mixdes.org); and an autumn Q3/2013 MOS-AK/GSA workshop in Bucharest, Romania.

About MOS-AK/GSA Modeling Working Group:

In January 2009, GSA merged its efforts with MOS-AK, a well-known industry compact modeling volunteer group primarily focused in Europe, to re-activate its Modeling Working Group. Its purpose, initiatives and deliverables coincide with MOS-AK's purpose, initiatives and deliverables. The Modeling Working Group plays a central role in developing a common language among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact model standardization and related tools for model development, validation/implementation and distribution.www.gsaglobal.org/working-groups/analog-mixed-signal 

About GSA:

The Global Semiconductor Alliance mission is to accelerate the growth and increase the return on invested capital of the global semiconductor industry by fostering a more effective ecosystem through collaboration, integration and innovation. It addresses the challenges within the supply chain including IP, EDA/design, wafer manufacturing, test and packaging to enable industry-wide solutions. Providing a platform for meaningful global collaboration, the Alliance identifies and articulates market opportunities, encourages and supports entrepreneurship, and provides members with comprehensive and unique market intelligence. Members include companies throughout the supply chain representing 30 countries across the globe.www.gsaglobal.org

Bookmark the permalink.

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Tuesday, 2 October 2012

[mos-ak] C4P: 5th International MOS-AK/GSA Workshop in San Francisco, Dec. 12, 2012

Together with the Organizing Committee and Extended MOS-AK/GSA TPC Committee, we have pleasure to invite to the 5th International MOS-AK/GSA Workshop in San Francisco, Dec. 12, 2012 http://www.mos-ak.org/sanfrancisco_2012/ The event will be organized in timeframe of the IEDM and CMC meetings.

Venue:
730 Montgomery Street
San Francisco, CA 94111, USA

Important Dates:
  • Call for Papers - Oct. 2012
  • Submission deadline - Nov. 15, 2012
  • Final Workshop Program - Nov. 30 2012
  • MOS-AK/GSA Workshop - Dec. 12, 2012

R&D Topics to be covered include the following:
  • Advances in semiconductor technologies and processing
  • Compact Modeling (CM) of the electron devices
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • CM of passive, active, sensors and actuators
  • Emerging Devices, CMOS and SOI-based memory cells
  • Microwave, RF device modeling, high voltage device modeling
  • Nanoscale CMOS devices and circuits
  • Technology R&D, DFY, DFT and IC Designs
  • Foundry/Fabless Interface Strategies

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[mos-ak] MOS-AK/GSA Bordeaux workshop on-line publications

The MOS-AK/GSA Modeling Working Group, a global compact modeling standardization forum, has delivered 10th subsequent compact modeling workshop which was organized on Sept. 21, 2012 as an integral part of the ESSDERC/ESSCIRC Conference in Bordeaux (F). The event was organized receiving full organization sponsorship provided by the leading industrial partners including Agilent Technologies (USA), LFoundry (D), CSEM (CH), STMicroelectronics (F), and AMS (A). The French Branch of IEEE EDS, FP7 COMON Project, Eurotraining and MOSIS Services were among the workshop technical program promoters. More than 50 international academic researchers and modeling engineers attended three sessions to hear 16 technical compact modeling talks and poster presentations.

The workshop's three sessions focused on the nanowire TFET and organic TFT technologies, advanced compact modeling for analog/RF IC design application, computer-aided design (CAD), EDA simulations highlighting recent developments of Verilog-A compact models and its standardization. The 10th MOS-AK/GSA ESSDERC/ESSCIRC workshop was opened by fifth invited female researchers highlighting active women contribution to compact modeling R&D. Afterward invited international modeling experts presented their recent modeling work. The session oral and poster presentations are available for download at http://mos-ak.org/bordeaux/

The MOS-AK/GSA Modeling Working Group coordinates several upcoming modeling events: 

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Thursday, 13 September 2012

Power & Performance: GSS Sees SOI Advantages for FinFETS

Posted by Adele HARS on August 31, 2012, at Advanced Substrate News

Power & Performance: GSS Sees SOI Advantages for FinFETS


Are FinFETs better on SOI? In a series of papers, high-profile blogs and subsequent media coverage, Gold Standard Simulations (aka GSS) has indicated that, yes, FinFETs should indeed be better on SOI.
To those of us not deeply involved in the research world, much of this may seem to come out of nowhere.  But there’s a lot of history here, and in this blog we’ll take a look at what it’s all about, and connect a few dots.

The GSS IEDM ’11 Paper

GSS is a recent spin-off of Scotland’s University of Glasgow – but there’s nothing new to the research community about these folks.  The core GSS-U.Glasgow team has been presenting important papers on device modeling at IEDM (which is one of the most prestigious of our industry’s conferences) and elsewhere for many years.
At the risk of stating the obvious, accurate simulations are incredibly important. Technologists need to be able to predict what results they can expect from different possible transistor design options before selecting the most promising ones.  Then they also need to provide reliable models to designers who will use them before committing chips to silicon.  One of the biggest challenges is predicting variability, which as we all know is getting worse as transistors scale to ever-smaller dimensions.
At IEDM ’11 last December, GSS-U.Glasgow presented Statistical variability and reliability in nanoscale FinFETs.  This covered  “A comprehensive full-scale 3D simulation study of statistical variability and reliability in emerging, scaled FinFETs on SOI substrate with gate-lengths of 20nm, 14nm and 10nm and low channel doping…”.  Essentially they concluded that scaling FinFETs on SOI should be no problem – and in fact the statistical variability of a 10nm FinFET on SOI would be about the same as the industry’s currently seeing in 45nm bulk CMOS.
That paper was based on work that the GSS-U.Glasgow team had done on two major European projects: the EU ENIAC MODERN project, and the EU FP7 TRAMS project.  It’s perhaps worth looking a little more closely at what those projects are about – and who’s involved:
  • A key objective of the MODERN (for Modeling and Design of Reliable, process variation-aware Nanoelectronic devices, circuits and systems) is to develop “effective methods for evaluating the impact of process variations on manufacturability, design reliability and circuit performance”.  Other partners in the project include ST, Leti, NXP, Infineon, Numonyx (now Micron) and Synopsys.
  • The objective of the TRAMS (for ‘Tera-scale Reliable Adaptive Memory Systems’) project is “to investigate in depth potential new design alternatives and paradigms, which will be able to provide reliable memory systems out of highly unreliable nanodevices at a reasonable cost and design effort”. Other partners in the project include Intel, imec, and UPC/BarcelonaTech.

READ MORE AT THE SOURCE

Sunday, 2 September 2012

CMRF Workshop (at BCTM)


CMRF Workshop (at BCTM)
Wednesday October 3, 2012, in Portland, Oregon, USA

Session Chair: Colin McAndrew
As with previous years the Workshop on Compact Modeling for RF/Microwave Applications (CMRF) is being held in conjunction with BCTM. The workshop has an interactive dynamic, and this year includes a Forum of experts who will assess the present major needs in modeling.

1:00–1:30 PM – Advanced SiGe HBT Modeling with HICUM Level 0 (v1.3) for RF and mmW Applications
D. Celi and N. Derrier
This presentation deals with advanced bipolar modeling using the latest revision of HICUM/L0 (1.3). Following an overview of test structures and measurement setup used for bipolar transistors, the new HICUM/L0 formulations are described. Subsequently a workflow for parameter extraction is detailed that is suitable for advanced SiGe heterojunction bipolar transistors for mmW applications. As a last point the possibilities and limitations of the model and the parameter extraction are discussed.

1:30–2:00 PM – Dynamic Ageing Modeling for Reliability Simulation
B. Ardouin
Semiconductor device behavior is not static but changes over time, and the amount of change depends on details of the voltages and currents a device experiences. This presentation will review recent development of a dynamic ageing model for HiCuM 2.3 and provides details of Verilog-A implementation and pragmatic modeling issues related to self-consistent integration of transistor degradation in accelerated time based on realistic transient circuit operation.

2:00–2:30 PM – End-to-End Modeling for Handset Power Amplifiers – It’s Not Just Two Transistors!
P. Zampardi, Y. Yang, K. Kwok, B. Li, A. Metzger, C. Cismaru, H. Shao, W. Sun, and M. Fredriksson
The short design cycle for handset power amplifiers relies on accurate models for ALL components used in the design, not just the “two HBTs” used for the power transistors. As the complexity of these amplifiers (usually used in front-end modules) has increased, so has the required accuracy for simulating the package, control circuitry, and the RF chain itself. This presentation will show some of the challenges and solutions developed to address the development of high-yield commercial power amplifiers and the design flow for their realization.

2:50–3:20 PM – Practical Modeling: When Less is More
A. DiVergilio
The primary goal of compact modeling is to allow designs to be carried out quickly and efficiently. Therefore, model accuracy is not the only metric of model effectiveness. No matter what the circuit, significant portions of the design cycle can benefit more from rapid iteration than from absolute accuracy. Overly-complicated models slow down simulation and, at worst, prevent convergence all-together, especially for large designs. This presentation discusses trade-offs that can be made between speed and accuracy, emphasizing the flexibility that can be achieved through high-level modeling languages, such as Verilog-A, when applied to device-level model development.

3:20–4:20 PM – Forum: “Grand Challenges in Modeling”
Queen Marie Ballroom
Models are by definition imperfect, but what are the biggest opportunities for improvement that will have the biggest bang-for-the-buck in design? This forum will attempt to answer that question, and formulate a prioritized list of items that will be published on the BCTM web site.

Participants:

  • Bertrand Ardouin (XMOD technologies)
  • Adam DiVergilio (Tektronix)
  • Mikhail Shirokov (Triquint Semiconductor)
  • Peter Zampardi (Skyworks Solutions)
  • Colin McAndrew (Moderator; Freescale)

Monday, 13 August 2012

CTFT 2012


4th International Workshop on Compact Thin-Film Transistor (TFT) Modeling for Circuit Simulation

This workshop will provide a forum for discussions and current practices on compact TFT modeling. The workshop is sponsored by IEEE EDS Compact Modeling Technical Committee in joint collaboration with Cambridge University. A partial list of the areas of interest includes:

  • Physics of TFTs and operating principles
  • Compact TFT device models for circuit simulation
  • Model implementation and circuit analysis techniques
  • Model parameter extraction techniques
  • Applications of compact TFT models in emerging products
  • Compact models for interconnects in active matrix flat panels

The workshop organizers:
Department of Engineering, University of Cambridge, Cambridge, UK
Technical School of Engineering, University Rovira i Virgili, Tarragona, Spain

Tuesday, 24 July 2012

[mos-ak] Final Program: 10th MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Bordeaux, Sept. 21, 2012

Together with the Organizing Committee, Extended MOS-AK/GSA TPC Committee, and the IEEE EDS French Branch, the technical program sponsor, as well as with the industrial sponsors Agilent Technologies, LFoundry, CSEM, STM, AMS we have pleasure to invite to the 10th MOS-AK/GSA Compact Modeling Workshop at the ESSDERC/ESSCIRC Conference in Bordeaux, Sept. 21, 2012.  

The final workshop program is available on-line: <http://mos-ak.org/bordeaux/

To register please visit official ESSDERC/ESSCIRC registration website.

- with regards - WG (for the MOS-AK/GSA Committee
––––––––––––––––––––––––––––––––––---------------- 
MOS-AK/GSA Bordeaux (F) Sept.21, 2012 
MOS-AK/GSA San Francisco, CA Q4 2012 
––––––––––––––––––––––––––––––––––---------------- 

Why- and how- to integrate Verilog-A compact models in SPICE simulators

A nice paper from Maria-Anna Chalkiadaki, Cédric Valla, Frédéric Poullet, and Matthias Bucher:

Why- and how- to integrate Verilog-A compact models in SPICE simulators

This article presents a fast and accurate way to integrate and validate Verilog-A compact models in SPICE-like simulators. Modifications in the models' Verilog-A source code may be required prior to their conversion into low-level C language by a code generator. The most common of these modifications is discussed. The generated C code is then directly compiled in the target simulator resulting in an equivalent SPICE model. The comparison between Verilog-A and SPICE models in the same simulation environment, for simple and complex circuits, validates the procedure. Performance tests for demanding designs are carried out for both models. Results highlight the higher simulation speed and lower memory consumption of SPICE models. Copyright © 2012 John Wiley & Sons, Ltd.

Sunday, 8 July 2012

Birthday (61) of the JUNCTION transistor

From EDN:


Bell Labs and primarily William Shockley announced the invention of the junction transistor at a press conference in Murray Hill, NJ, the first week of July, 1951.
Sources vary as to when the formal announcement was actually made, July 4, 1951, or July 5, 1951.
At the time, Shockley was with Bell Labs’ solid state physics group, a unit to which he was a group head and a unit that saw much internal competition.
This new type of transistor overcame problems created by earlier point-contact transistors, developed by Bell Labs’ Joe Bardeen and Walter Brattain without Shockley but based in part on his previous work. It is said that when the patent process began for the point-contact transistor, Shockley made an effort to have his name only placed on the patent and made sure his fellow engineers knew of that effort.
Shockley has been described as having a “tremendous ego” by his co-workers. He was also known as having openly racist views.
Although Shockley is often known as “the inventor” of the transistor and despite his reported ego, he was often noted as correcting such misstatement and noting that he led the effort with others involved. Notes made during the development of the junction transistor can be viewed here.
Shockley left Bell Labs a few years after working on the junction transistor and eventually became a professor emeritus of electrical engineering at Stanford. He died on campus in 1989 at the age of 79.

For more moments in tech history, see this blog.

Monday, 2 July 2012

NANOTEC-Tutorial at ESSCIRC/ESSDERC in Bordeaux on 09/17/2012

The NANO-TEC project will held a half day tutorial at the ESSDERC/ESSCIRC Conference in Bordeaux on Monday, September 17, 2012. This Tutorial will be on the ECOSYSTEMS TECHNOLOGY and DESIGN for NANOELECTRONICS in Europe and will present the current outcome of the EU project NANOTEC [read more...]

Thursday, 21 June 2012

[mos-ak] C4P: Special Issue of IEEE TED on Advanced Modeling of Power Devices and Their Applications

Call for Papers
For the Special Issue of
IEEE Transactions on Electron Devices 
On
Advanced Modeling of Power Devices and Their Applications

The special issue on "Advanced Modeling of Power Devices and Their Applications" is devoted to the research and development activities on power devices, the correlation of modeling approaches to the physics of power devices and in particular on emerging models of advanced power devices for power circuit applications. 

The importance of accurate circuit design with power devices is increasing according to the necessity of realizing efficient energy consumption. High-voltage MOSFETs are also utilized in all kinds of consumer electronics, and electric vehicles are controlled by IGBT circuit, where an urgent task is to achieve better energy control at about 1 kV bias condition. Accurate and even predictable models based on a close correlation to the important physical effects occurring in such power devices are therefore highly desired for precise circuit design. Presently many investigations are also undertaken intensively for new materials such as SiC and GaN replacing Silicon for extremely high voltage applications e.g. beyond 10 kV. A good understanding of the device operation under such extremely high bias conditions requires a lot physical analysis, and as a result leads to more effective utilization of these power devices. Together with the strong self-heating effect, the dynamically changing resistivity makes convergence in circuit simulation unstable. Techniques and physical analysis to overcome such problems are also urgently requested. 

Due to the wide range of covered bias conditions and the large variety of device structures applied, a lack of  communication occurs in the high-voltage community even though the basic tasks are the same. Therefore, the objective of this special issue is to bring together a diversity of R&D activities and advancements in the physical analysis and modeling of MOS-based power devices and other types of emerging power devices including Bipolar, Thyristor and Diode. Models for active and passive components integrated in advanced silicon as well as new material technologies, statistical modeling and mixed-mode simulation are also of special interest. 

The requirements for modeling high-voltage devices on the part of the circuit design community are now much more demanding due to urgent necessity to reduce energy consumption, where the high-voltage devices play an important role. Submissions should address advances in device characterization, physical models, as well as applications preferably but not limited to the following areas:
1. Compact modeling of power devices such as high-voltage MOSFETs, Bipolar, Thyristor and IGBT for 
circuit applications from a few volts up to beyond 10kV.
2. Modeling of passive elements such as Diode, Inductor, Resistor.
3. Investigations on new material such as SiC and GaN and their applications.
4. Circuit simulation for real applications of power devices together.
5. Investigation for computation efficiency for circuit simulation

Please submit manuscript by using the following:
http://mc.manuscriptcentral.com/ted

MAKE SURE TO MENTION THE SPECIAL ISSUE IN THE COVER LETTER
Paper Submission Deadline: July 15, 2012 
Scheduled Publication Date: February, 2013 

Guest Editors: 
Mitiko Miura-Mattausch, Hiroshima University, mmm@hiroshima-u.ac.jp  
Narain Arora, Silterra Malaysia, narain@silterra.com
Ehrenfried Seebacher,  Austriamicrosystems AG, ehrenfried.seebacher@austriamicrosystems.com
Samar K. Saha, SuVolta, Inc., samar@ieee.org

If you have any questions about submitting a manuscript, please contact:
IEEE EDS Publications Office
445 Hoes Lane Piscataway NJ 08854
Phone: +1 732 562 6855   Fax: +1 732 562 6831

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Wednesday, 20 June 2012

5th "Micro&Nano2012" Kokkini Hani, Heraklion, 7-10 October 2012

Fifth International Conference "Micro&Nano2012"
on Micro - Nanoelectronics, Nanotechnologies and MEMs
Aquis Arina Sand Hotel, Kokkini Hani, Heraklion
7-10 October 2012

This is the first Micro&Nano conference, which will be organized at Heraklion, Grete, by members of the Micro&Nano society affiliated with the Foundation for Research and Technology (FORTH) and University of Crete. The conference will be co-chaired by Dr. Georgios Konstantinidis and Prof. Alexandros Georgakilas.

The Conference combines an extensive scientific programme including oral and poster sessions with exhibition and social events.

The Conference aims at gathering together in an interactive forum all scientists and engineers working in the challenging areas of micro/nano-electronic and optoelectronic/photonic devices, MEMs and circuits, as well as the enabling nanotechnologies of material growth, synthesis and processing. It aims to stimulate discussions on the last achievements and new developments in this rapidly evolving field.

One of the key objectives of the Conference is to promote collaboration and partnership between different academia, research and industry players. A one day workshop, presenting indicative cases and reviewing experiences and perspectives in these domains in Greece and elsewhere, will follow the conference [read more...]

The Scariest Graph

Posted from SemiWiki:



The Scariest Graph I've Seen Recently

Everyone knows Moore's Law: the number of transistors on a chip doubles every couple of years. We can take the process roadmap for Intel, TSMC or GF and pretty much see what the densities we will get will be when 20/22nm, 14nm and 10nm arrive. Yes the numbers are on track.

But I have always pointed out that this is not what drives the semiconductor industry. It is much better to look at Moore's Law the other way around, namely that the cost of any given functionality implemented in semiconductors halves every couple of years. It is this which has meant that you can buy (or even your kid can buy) a 3D graphics console that contains graphics way beyond what would have cost you millions of dollars 20 years ago in a state of the art flight simulator.

But look at this graph:


This shows the cost for a given piece of functionality (namely a million gates) in the current process generation and looking out to 20nm and 14nm. It is flat (actually perhaps getting worse). This might not matter too much for Intel's server business since those have such high margins that they can probably live with a price that doesn't come down as much as it has done historically. And they can make real money by putting more and more onto a chip. But it is terrible for businesses like mobile computing that don't live on the bleeding edge of the maximum number of transistors on a chip. If you are not filling up your 28nm die and a 20nm die costs just the same (and is much harder to design) why bother? Just design a bigger 28nm die (there may be some power savings but even that is dubious since leakage is typically an increasing challenge).

If this graph remains the case, then Moore's Law carries on in the technical sense that you can put twice as many transistors on your chip if you can think of something clever to do with them and can find a way to keep enough of them powered on. But it means there is no longer an economic driver to move to a new process unless you have run out of space on the old one.

Since EDA mostly makes money on designs in new processes (because they need new tools which can be sold at a premium) this is bad for EDA. It actually doesn't make money on the first few designs coming through a new process because there is so much corresponding engineering to be done. But if the mainstream never moves, the cash-cow aspect of selling EDA tools to the mainstream won't happen. And just like there is no business selling "microprocessor design tools" since there are too few groups who would buy them and their needs are too different, there might never be a big enough market for "14nm design tools" to justify the investment.

So that's why this is the scariest graph in EDA.

Monday, 18 June 2012

[mos-ak] [2nd announcement] 10th MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Bordeaux, Sept. 21, 2012

[2nd announcement] 10th MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Bordeaux, Sept. 21, 2012
http://mos-ak.org/bordeaux/

Together with the Organizing Committee, Extended MOS-AK/GSA TPC Committee, and the IEEE EDS French Branch, the the technical program sponsor, we have pleasure to invite to the 10th MOS-AK/GSA Compact Modeling Workshop at the ESSDERC/ESSCIRC Conference in Bordeaux, Sept. 21, 2012.  

Free on-line registration (open on June 18) 
http://www.mos-ak.org/bordeaux/registration.php

The terms of participation, intending participants and authors should also note the following dates: 
  • Preannouncement - April 2012
  • Call for Papers - May 2012
  • Abstract submission deadline - July 2012
  • Final Workshop Program - Aug. 2012
  • MOS-AK/GSA Workshop - Sept. 21, 2012 http://www.mos-ak.org/bordeaux/
    • Morning Session
    • Panel Discussion: "Status and Next Decade of European Compact Modeling"
    • Poster Session 
    • Afternoon Session
Speakers (tentative list): 
Prof. Maria Helena Fino, Universidade Nova Lisboa, P
Prof. Lidia Lukasiak, TU Warsaw, PL
Prof. Androula Nassiopoulou, IMEL Demokritos, GR
Prof. Elena Gnani, University of Bologna, I
Munira Raja. Uni. Liverpool, UK
Maria-Alexandra Paun, EPFL, CH
Sadayuki Yoshitomi, Toshiba, JP
Yogesh S. Chauhan, UC Berkeley, USA
Patrick Martin, Minatec, F
Daniel Tomaszewski, ITE Warsaw, PL

Further details and updates: <http://mos-ak.org/bordeaux/
Email contact: <workshops@mos-ak.org

- with regards - WG (for the MOS-AK/GSA Committee
––––––––––––––––––––––––––––––––––---------------- 
COMON Tranining Course Tarragona (SP) June 28-29, 2012
MOS-AK/GSA Bordeaux (F) Sept.21, 2012 
MOS-AK/GSA San Francisco, CA Q4 2012 
––––––––––––––––––––––––––––––––––---------------- 

Special IETE issue on Compact Modeling

Special IETE issue (May-June 2012 Volume 58; Issue 3 Page Nos. 179-242) on Compact Modeling: "Compact Modeling as a Bridge between Scaled Semiconductor Technologies and Advanced Designs of the Integrated Circuits" is available on-line with following articles:
  1. A Hybrid Verilog-A and Equation-defined Subcircuit Approach to MOS Switched Current Analog Cell Simulation p. 181
    Mike E Brinson, Stefan Jahn, H Nabijou
  2. Aging Model for a 40 V Nch MOS, Based on an Innovative Approach p. 191
    Filippo Alagi, Roberto Stella, Emanuele Viganó
  3. Complex 2D Electric Field Solution in Undoped Double-gate MOSFETs p. 197
    Mike Schwarz, Thomas Holtij, Alexander Kloes, Benjamín Iñíguez
  4. 2D Analytical Calculation of the Parasitic Source/Drain Resistances in DG-MOSFETs Using the Conformal Mapping Technique p. 205
    Thomas Holtij, Mike Schwarz, Alexander Kloes, Benjamín Iñíguez
  5. RF Compact Modeling of High-voltage MOSFETs p. 214
    Antonios Bazigos, François Krummenacher, Jean-Michel Sallese, Matthias Bucher, Ehrenfried Seebacher, Werner Posch, Kund Molnár, Mingchun Tang
  6. HSPICE Model of the Physical Resistor p. 222
    Petr Beták, Petr Zavrel
  7. Enhanced Non-quasi-static Lauritzen Diode Model p. 226
    Lenka Sochová, Petr Beták, Ján Plojhár
  8. Self-heating Parameter Extraction of Power Metal-oxide-silicon Field Effect Transistor Based on Transient Drain Current Measurement p. 230
    Risho Koh, Takahiro Iizuka
  9. Extraction of Scalable Electrical Model for HV (600/800 V) MOS Transistors p. 237
    Lorenzo Labate, Simona Angela Cozzi, Roberto Stella

Sunday, 10 June 2012

450mm Impact Report Now Available For Free Download

This unique and authoritative report identifies the activities required to attract investments and to support 450mm and other advanced research, innovation, prototyping and semiconductor production. This report was based on a 14-month study Future Horizons undertook, together with the French market research firm Decision, between January 2011 and February 2012.

A copy of the report can be downloaded from the Commission's website at: http://cordis.europa.eu/fp7/ict/nanoelectronics/documents/450mm-final-report.pdf

If you have any questions on the report on some of the wider 450mm issues, please do so via our website at www.futurehorizons.com or call +44 1732 740440.

Wednesday, 6 June 2012

[mos-ak] 2nd Training Course on Compact Modeling: Registration Open

The MOS-AK Group as main dissemination partner of the European COMON Compact Modeling Network is announcing series of the modeling events:
Visit also the compact modeling calendar at www.mos-ak.org

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Tuesday, 5 June 2012

10th Graduate Student Meeting on Electronic Engineering in Tarragona (Spain)

The Graduate Student Meeting on Electronic Engineering, has been an annual event, created and organized by the Department of Electronic, Electrical and Automatic Control Engineering of the Universitat Rovira i Virgili (URV, Tarragona, Spain) since 2003. Consist of two days of plenary talks given by invited prestigious researchers about selected topics related to electronic engineering, short talk given by last year Doctoral students presenting their last research results and a poster sessions were master and PhD students in this field presented their work. With this format, the Graduated Student Meeting has become a very useful forum for Master and PhD students as well as researchers in the field of Electronic Engineering.

The 10th  Graduate Student Meeting on Electronic Engineering will be held at the Campus of the Universitat Rovira (Tarragona, Spain) from June 22 to 23 2012. Registration is free.

So we encourage graduated students working in the topics:
  • Nanoelectronics and Nanophotonics
  • Micro and Nanosystems
  • Power Electronics & Renewable Energy Systems
  • Signal Processing and Data Mining
  • Automatic Control
To submit their recent work to be considered for acceptance and published in the book of Abstracts of the Meeting. The deadline for abstracts reception is June 8th.

Registration is free!

The invited lectures and lecturers will be:

Thermal modeling and simulation
Dr. Goce Arsov,, Ss Cyril and Methodius University, Skopje, Macedonia

Analysis of a chaotic motion of a linear switched reluctance motor
Dr. Bruno Robert, Université de Reims Champagne-Ardenne, France

Hydrothermal synthesis and the Influence of Hydrothermal Reaction Parameters on the Morphology and Dimensions of Sodium Titanate and MnO2 nanostructures
Dr. Polona Umek, Jožef Stefan Institute, Ljubljana, Slovenia

Advances in Nanoelectronics and Functional Diversifications
Dr. Simon Deleonibus, CEA-LETI, MINATEC, Grenoble 38054, France

Knowledge Discovery by Accuracy Maximization
Dr. Stefano Cacciatore, CERM, University of Florence, Italy

Porous silicon for the construction of biosensors and for biomedical applications
Dr. Frédérique Cunin, Institut Charles Gerhardt Montpellier, France


As you can see, some of the lectures are related to device modeling.

Besides, the 10th Graduate Student Meetiong will be held in conjunction with two more interesting events, which also will take place in Tarrgona:

1) The 8th International Conference on Organic Electronics (ICOE): June 25-27 2012.

2) The 2nd Training Course on Compact Modeling (TCCM), June 28-29 2012.







2nd Training Course on Compact Modeling: Registration open

Building on the success of its first edition in 2012, the 2nd Training Course on Compact Modeling (TCCM) will be held in Tarragona (Catalonia, Spain) on June 28-29 2012. It will be organized by will be organized by the NEPHOS Group, of the Department of Electronic, Electrical and Automatic Control Engineering at the Universitat Rovira i Virgili (Tarragona).. The General Chairman is Prof. Benjamin Iñiguez.



The Training Course on Compact Modeling will consist of 12 of lectures addressing relevant topics in the compact modeling of advanced electron devices. These lectures will be conducted by top experts in the field. Most of the lectures will target compact modeling issues applicable to many electron devices. In particular, emphasis will be given on MOSFETs (bulk, SOI, Multi-Gate and High Voltage MOS structures) and HEMTs.


REGISTRATION IS OPEN. It is quite cheap:



Advanced Registration (before June 16)
Students: 100 euro
Non-Students: 130 euro
COMON Members: FREE


On-Site Registration (after June 16)
Students: 150 euro
Non-Students: 180 euro
COMON Members: FREE


NOTE: The gala dinner is included in the registration price.
 Registration includes lunches, coffe breaks and a Gala Dinner on June 28, in a nice restaurant with TV screens to watch the Semifinals match of the Soccer European Cup ...

There will be a 50% discount for all members that participate in the SQWIRE FP/ EU project, as well as the participants to the 8th International Conference on Organic Electronics (ICOE 2012).


The Training Course on Compact Modeling is an event sponsored by the FP7 “COMON” (COmpact MOdelling Network) IAPP Project (which is coordinated by the Universitat Rovira i Virgili) in collaboration with the IEEE EDS Compact Modeling Technical Committee.

The programme of the 2nd Training Course on Compact Modeling is:



Thursday, June 28
   
8:30 Benjamin Iñiguez - Universitat Rovira i Virgili (Tarragona, Spain)
  Training Courses Opening Session
   
8:55 Raphaël Clerc - Institut National Polytechnique de Grenoble (Grenoble, France)
  "Tunnel and quasi-ballistictransport modelling in nanoscale MOS devices"
   
10:05 Jamal Deen - McMaster University (Hamilton, Ontario, Canada)
  "High frequency noise modeling"
   
11:15 Coffee Break
   
11:40 Romain Ritzenthaler - IMEC (Leuven, Belgium)
  "3D analytical modelling techniques for Tri-Gate MOS structures"
   
12:50 Franz Sischka - Agilent Technologies (Böblingen, Germany)
  "S-parameter and nonlinear RF modelling"
   
14:00 Lunch
   
15:15 Frédéric Martinez - Université de Montpellier 2 (Montpellier, France)
  "Low frequency noise modeling"
   
16:25 David Jiménez - Universitat Autònoma de Barcelona (Barcelona, Spain)
  "Quantum confinement models for nanoelectronic devices"
   
20:30 Gala Dinner
   
   
Friday, June 29
   
8:45 Giovanni Ghione - Politecnico di Torino (Torino, Italy)
  "Thermal modelling of RF and microwave devices"
   
9:55 Colin C. McAndrew - Freescale Semiconductors (Phoenix, AZ, USA)
  "Statistical modelling techniques"
   
11:05 Coffee Break
   
11:30 Antonio Cerdeira - CINVESTAV (Mexico D.F., Mexico)
  "Design-oriented compact modelling for Multi-Gate MOS devices"
   
12:50 Mike Brinson - Metropolitan University of London (London, UK)
  "QucsStudio: A second generation Qucs software package for compact semiconductor devicemodel development based on interactive and compiled equation-defined modellingtechniques plus circuit simulation"
   
14:00 Lunch
   
15:15 Thomas Gneiting - AdMOS GmbH (Frickenhausen, Germany)
  "Flicker noise measurements and characterization"
   
16:25 Peter Lee - Elpida Memory (Japan) and vice-chair of the Compact Modeling Council
  "World-wide Model Standardization at the CMC, and DRAM Modeling Needs"
   
17:35 Conclusions and announcements
 


Besides, on June 25-27 the same group at URV will organize 8th International Conference on Organic Electronics (ICOE 2012) also in Tarragona. Participants to this Training Course will have a reduced fee for ICOE 2012.


Last but not least, the 10th Graduate Student Meeting on Electronic Engineering will be hels at URV Campus, Tarragona, from June 21 to 22. This event consist of two days of plenary talks given by invited prestigious researchers about selected topics related to electronic engineering, short talk given by last year Doctoral students presenting their last research results and a poster sessions were master and PhD students in this field presented their work. With this format, the Graduated Student Meeting has become a very useful forum for Master and PhD students as well as researchers in the field of Electronic Engineering.



Therefore, if you are interested in the three events, you can stay in Tarragona from June 22 to 29, and spoend the weekend there. The night from June 23 to 24 is the St. John's eve, which is well celebrated in Tarragona (in particular, on the beach) as well as in the rest of Catalonia.


Tarragona is located in the south of Catalonia, in the northeast corner of the Iberian Peninsula. Tarraco (its Roman name) was one of the most important cities in the Roman Empire.
On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tàrraco a World Heritage Site.

Tarragona can be easily reached from Barcelona Airport by bus and train. It is about 100 Km South from Barcelona. Besides, Reus Airport (less than 15 Km from Tarragona) receives flights from many European cities in the summer.

Tarragona can be easily reached from Barcelona Airport by bus and train. It is about 100 Km South from Barcelona. Besides, Reus Airport (less than 15 Km from Tarragona) receives flights from many European cities in the summer.

Speaking about Tarraco's climate, the famous Roman poet Virgil wrote: "The climate blends and confuses the seasons singularly, so that all the year seems an eternal spring." Thanks to its temperate climate, with an average yearly temperature of 23ºC, its clean beaches with fine and gloden sand, and its singular artistic and architectural heritage, Tarragona is one of the most important tourism hubs in Europe.

I strongly encourage all people interested in compact modeling to attend the 2nd Training Course on Compact Modeling!

Friday, 18 May 2012

Intel's FinFETs are less fin and more triangle

EE Times staff -- EDN, May 17, 2012

LONDON -- Reverse engineering and analysis consultancy Chipworks Inc  has posted microscope cross-sections of parts of the 22-nm Ivy Bridge processor from Intel that has revealed that the FinFETs, which Intel calls tri-gate transistors, are in fact trapezoidal, almost triangular, in cross-section.

The ICs were 64-bit, four-core Xeon E3-1230 CPUs intended for the server market, which Chipworks (Ottawa, Ontario) said it obtained in Hong Kong, China.

The triangular section is markedly different to the idealized rectangular section that Intel had shown previously in 2011. However, it is not clear whether the non-vertical sides to the fins are a non-critical manufacturing artifact or are deliberately engineered by Intel and have a critical impact on electron mobility or yield.

Gold Standard Simulations Ltd (or GSS base in Glasgow, Scotland), a spin-off from the University of Glasgow led by Professor Ase Asenov as CEO, responded by saying on its Web site: "There is a lot of speculation about the possible advantages and disadvantages of the trapezoidal, or almost triangular, shaped 'bulk' FinFET." GSS has performed a simulation analysis of the FinFET using its statistical 3-D TCAD simulator called Garand.



  EET_Intel_051712




EET_Intel2_051712


Comparison of the TEM image of one of the FinFETs from Figure 6 of the Chipworks blog (linked above) with the Garand simulation domain of Gold Standard Simulations. 

 
GSS' simulation was used to explore the dependence of threshold voltage on gate length for the trapezoidal Intel transistor and an equivalent rectangular-fin transistor. "Clearly the rectangular fin has better short channel effects. Still, the million-dollar question is if the almost-triangular shape is on-purpose design, or is this, what bulk FinFET technology can achieve in terms of the fin etching?"

The comparisons between dimensionally comparable rectangular and trapezoidal FinFETs are not markedly different but as GSS had no knowledge of doping profiles it assumed a lightly doped channel. At the same time GSS acknowledged that there is a high doping concentration stopper below the fin in the shallow trench isolation (STI) region. "Clearly FinFETs are more complicated devices in terms of understanding and visualization compared to the old bulk MOSFETs," GSS concluded.

This story was originally posted by EE Times.

Thursday, 17 May 2012

[mos-ak] C4P 10th MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Bordeaux, Sept. 21, 2012

C4P 10th MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Bordeaux, Sept. 21, 2012
http://mos-ak.org/bordeaux/

Together with the Organizing Committee and Extended MOS-AK/GSA TPC Committee, we have pleasure to invite to the 10th MOS-AK/GSA Compact Modeling Workshop at the ESSDERC/ESSCIRC Conference in Bordeaux, Sept. 21, 2012.  

The terms of participation, intending participants and authors should also note the following dates: 
  • Preannouncement - April 2012
  • Call for Papers - May 2012
  • Abstract submission deadline - June 2012
  • Final Workshop Program - July 2012
  • MOS-AK/GSA Workshop - Sept. 21, 2012
Further details and updates: <http://mos-ak.org/bordeaux/
Email contact: <workshops@mos-ak.org

- with regards - WG (for the MOS-AK/GSA Committee
––––––––––––––––––––––––––––––––––---------------- 
MIXDES Special Modeling Sesion Warsaw (PL) May 24-26, 2012
COMON Tranining Course Tarragona (SP) June 28-19, 2012 
MOS-AK/GSA Bordeaux (F) Sept.21, 2012 
MOS-AK/GSA San Francisco, CA Q4 2012 
––––––––––––––––––––––––––––––––––---------------- 

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Wednesday, 16 May 2012

[mos-ak] MOS-AK/GSA Dresden workshop on-line publications

MOS-AK/GSA Dresden workshop on-line publications are available, visit: 

The MOS-AK/GSA Modeling Working Group, a global compact modeling standardization forum, held its annual spring workshop on April 26-27, 2012 at the Design Automation Division EAS of the Fraunhofer Institute for Integrated Circuits IIS in Dresden, Germany. More than 50 international academic researchers and modeling engineers attended four sessions to hear 16 technical compact modeling talks and poster presentations. The MOS-AK/GSA Modeling Working Group organized the event supported by Joachim Haase Fraunhofer IIS/EAS in Dresden, and a complementary X-FAB clean room visit, poster session and open networking event was hosted by Alexander Petr, X-FAB in Dresden.

As a result of an unfolded compact modeling discussion, the MOS-AK Group followed recommendation of Alexander Petr, X-FAB, a member of the Extended MOS-AK/GSA Compact Modeling Committee, to create a compact modeling open directory (CMOD:http://mos-ak.org/open_dir/). The directory will list available SPICE/Compact models including Verilog-A models for an extensive range of the semiconductor devices. The MOS-AK/GSA Group believes that the CMOD initiative will also stimulate further compact model developments for inter domain technologies and multidisciplinary applications.

The MOS-AK/GSA Dresden Press Note can be found here: 
and selected workshop photos are here:

I hope, we would have a next chance to meet us with your academic and industrial partners at future MOS-AK/GSA modeling events (check the list below).

- with regards - WG (for the MOS-AK/GSA Committee
––––––––––––––––––––––––––––––––––---------------- 
MIXDES Special Modeling Sesion Warsaw (PL) May 24-26, 2012
COMON Tranining Course Tarragona (SP) June 28-19, 2012 
MOS-AK/GSA Bordeaux (F) Sept.21, 2012 
MOS-AK/GSA San Francisco, CA Q4 2012 
––––––––––––––––––––––––––––––––––---------------- 

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Friday, 11 May 2012

Programme of the 2nd Training Course on Compact Modeling

The 2nd Training Course on Compact Modeling (TCCM) will be held in Tarragona (Catalonia, Spain) on June 28-29 2012.
 It will be organized by the NEPHOS Group, of the Department of Electronic, Electrical and Automatic Control Engineering at the Universitat Rovira i Virgili (Tarragona)..
The General Chairman is myself, Prof. Benjamin Iñiguez.

The Training Course on Compact Modeling will consist of l2 lectures addressing relevant topics in the compact modeling of advanced electron devices. These lectures will be conducted by top experts in the field. Most of the lectures will target compact modeling issues applicable to many electron devices. In particular, emphasis will be given on MOSFETs (bulk, SOI, Multi-Gate and High Voltage MOS structures) and HEMTs.
Attendees will  get very useful information on the different aspects of advenced device modelling. This training course is therefore recommended to Master and Ph D students, as well as postdocs and early stage researchers in companies, and not necessarily doing research on modelling.

Here is the final programme of the Training Course on Compact Modeling



 8:30   Training Courses Opening Session
           Benjamin Iniguez (Universitat Rovira i Virgili, Tarragona, Spain)

8:55  "Tunnel and quasi-ballistic transport modelling in nanoscale MOS devices".
         Raphaël Clerc (Institut National Polytechnique de Grenoble, France)

11:15 Coffee break

11:40 "3D analytical modelling techniques for Tri-Gate MOS structures"
            Romain Ritzenthaler (IMEC, Belgium)

12:50 "S-parameter and nonlinear RF modelling"
            Franz Sischka (Agilent Technologies, Böblingen, Germany)

14:00   Lunch
15:15   "Low frequency noise modeling"
            Frédéric Martinez (Université de Montpellier 2, France)

16:25 Quantum confinement models for nanoelectronic devices
          David Jiménez (Universitat Autònoma de Barcelona, Spain)


20:30    Gala dinner
  

June 29 2012

8:45   "Thermal modelling of RF and microwave devices"
        Giovanni Ghione (Politecnico di Torino, Italy)

9:55  "Statistical modelling techniques"
        Colin C. McAndrew (Freescale Semiconductors, Phoenix, AZ, USA)

11:05  Coffee break

 
11:30 High frequency noise modeling
          Jamal Deen (McMaster University, Canada)

12:50  "QucsStudio: A second generation Qucs software package for compact semiconductor device model development based on interactive and compiled equation-defined modelling techniques plus circuit simulation"
           Mike Brinson (Metropolitan University of London, UK)

14:00   Lunch

15:15  "Flicker noise measurements and characterization"
           Thomas Gneiting (AdMOS GmbH, Frickenhausen, Germany)

16:25 "World-wide Model Standardization at the CMC, and DRAM Modeling Needs"
            Peter Lee (vice-chair of the Compact Modeling Council, Elpida Memory, Japan)





Look at:
http://compactmodelling.eu/tccm2_programme.php

The Training Course on Compact Modeling is an event sponsored by the FP7 “COMON” (COmpact MOdelling Network) IAPP Project (which is coordinated by the Universitat Rovira i Virgili) in collaboration with the IEEE EDS Compact Modeling Technical Committee.

  • Registration will be cheap, in particular before June 16 :
http://compactmodelling.eu/tccm2_registration.php and will include lunches, coffee breaks and a Gala Dinner on June 28th.