Wednesday, 29 June 2011

Arrays of indefinitely long uniform nanowires and nanotubes

Arrays of indefinitely long uniform nanowires and nanotubes

Nature Materials 10, 494–501 (2011)
doi:10.1038/nmat3038


http://www.nature.com/nmat/journal/v10/n7/full/nmat3038.html


It's frankly nice.... see one of their pictures (hope they don't get too upset!):

Thursday, 23 June 2011

SISPAD 2011 Companion Workshops

September 7, 2011; Hotel Hankyu Expo Park, Osaka, Japan
  • Compact Modeling
    • Organizer: Sadayuki Yoshitomi, Toshiba Corporation
  • Power Devices
    • Organizer: Ichiro Omura, Kyusyu Institute of Technology

SuVolta creates new transistor option for 20 nm

SuVolta creates new transistor option for 20 nm: "SuVolta, a startup process IP company with deep roots indevice design and m..."

Wednesday, 22 June 2011

Job offers at RF Micro Devices (RFMD)

I've seen that there are three job offers for Compact Modeling engineers at RFMD:

Tracking Code           Job Title             Location            Date Posted

12134 Senior Modeling Engineer Greensboro, NC, US 6/7/2011
12117 Sr. TCAD Modeling Engineer Greensboro, NC, US 5/26/2011
12116 Sr. Modeling Engineer Greensboro, NC, US 5/24/2011


Note that this is only a re-diffusion of some information we've got, and that we're not related to them in any way!

Friday, 17 June 2011

Get your own version of Myfab LIMS


Myfab is the Swedish national research infrastructrue for micro and nano fabrication. Use the best cleanroom facilities in Sweden through our laboratory network and bring new scope and opportunity to your research and technical development. [read more]


IMEC benchmarks FinFET superiority

IMEC benchmarks FinFET superiority:

By Peter Clarke, EE Times -- EDN, June 16, 2011

LONDON - The IMEC research institute has compared one planar and two FinFET technologies to see how they perform against scaling and process variability.

The benchmark circuits were six-transistor SRAM cells and SRAM arrays and IMEC has concluded that the FinFET outperforms planar CMOS in variability-aware and technology-aware comparison of SRAM product yield.

Both FinFET on bulk and FinFET on silicon-on-insulaor (SOIFF) technologies come out superior to the planar technology for medium- to large-sized SRAM arrays resulting in higher yields, IMEC said, although it did not disclose the process geometry at which the tests were done. It is likely to have been at around 28 to 22 nm.

As the dimensions of devices scale down, the variations in the electrical parameters of CMOS transistors steadily increase. This is due to random fluctuations in the density of the dopants in the channel, source, and drain. So, two closely placed transistors that are supposedly identical can show a widely different behavior. This makes the design of SRAM memory cells less predictable and controllable for every new technology node.

Because of this scaling 6T planar SRAMs below 22 nm remains challenging, IMEC said. FinFET devices show a lower leakage and variability and it is possible to design more compact cells.

Both FinFET technologies come out as superior to planar for SRAM arrays of greater than 128 kbytes. They are less sensitive to mismatches, thus allowing a more aggressive scaling of the power supply and a lower VCC than planar arrays. For undoped silicon-on-insulator FinFETs (SOIFF), the power supply can be lowered by an additional 200-mV compared to planar. As a sample result: undoped SOIFF FinFET allow for a 95% yield at 0.7-V in 32-Mbit SRAM arrays, moving to Gbit arrays for higher voltages.

Wednesday, 15 June 2011

A new birth in the IEEE journals world...

 
Let's welcome them! 
They are starting with some interesting papers on low-power and analog design with nanometer-scale variations.... Let's hope they go on... 
 
IEEE Journal of Emerging and Selected Topics in Circuits and Systems (JETCAS)

We are honored to welcome readers and authors to the inaugural issue of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS for short), which is sponsored by the IEEE Circuits and Systems Society (CAS-S.)

The journal, which is freely accessible on-line to all CAS-S members, aims to build a platform for the broad and timely dissemination of key innovative results and findings in rapidly-growing and/or emerging topic areas within the scope of the IEEE Circuits and Systems Society. Such potentially interdisciplinary emerging topics will be selected as long as, first, they are clearly situated at the forefront of current scientific and technological developments and, second, they are expected to grow over time in scientific and professional importance and, therefore, in the number of active practitioners. From this point of view, JETCAS is expected to create new communities interested in the long-term development of the most promising subjects presented in the journal. The editorial strategy followed by JETCAS will be the publication of Special Issues on the selected topics. These issues will include research contributions from leading experts and presentations geared towards a wide audience of scientists and pra

MASSOUD PEDRAM, Editor-in-Chief (EiC)

MANUEL DELGADO-RESTITUTO, Deputy EiC

ENRICO MACII, 2010-2011 VP Publications, IEEE CAS-S

GIANLUCA SETTI, 2010 President, IEEE CAS-S  


Volume 1, Issue 1 - Inaugural Edition
http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5503868

Pedram, M.;  Delgado-Restituto, M.;  Macii, E.;  Setti, G., Inaugural Editorial
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5765455

-----------------------------------------------------------------------------------------------------
Variation-Aware Design for Nanoscale VLSI Circuits and Systems
The focus of this issue is on the challenges faced in designing digital and analog circuits in nanoscale technologies, where variations due to process, environmental, and aging variations are substantial.  The root causes of these effects can generally be traced to scaling: with the drive towards even greater miniaturization, these problems become even more acute and it is imperative that they be addressed.  The solutions involve the invention of improved design techniques, better design automation, and closer interactions between the phenomenological root causes and the designer.  The six papers in this issue attempt to provide a view of the landscape, reflecting the current state of the art and future directions.

Sapatnekar, S. S., Guest Editorial
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5762378

------------------------------------------------------------------------------------------------------------------
Sapatnekar, S. S., Overcoming Variations in Nanometer-Scale Technologies
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5762377
Nanometer-scale circuits are fundamentally different from those built in their predecessor technologies in that they are subject to a wide range of new effects that induce on-chip variations. These include effects associated with printing finer geometry features, increased atomic-scale effects, and increased on-chip power densities, and are manifested as variations in process and environmental parameters and as circuit aging effects. The impact of such variations on key circuit performance metrics is quite significant, resulting in parametric variations in the timing and power, and potentially catastrophic failure due to reliability and aging effects. Such problems have led to a revolution in the way that chips are designed in the presence of such uncertainties, both in terms of performance analysis and optimization. This paper presents an overview of the root causes of these variations and approaches for overcoming their effects.
-----------------------------------------------------------------------------------------------------------------
Karakonstantis, G.;  Chatterjee, A.;  Roy, K., Containing the Nanometer "Pandora-Box": Cross-Layer Design Techniques for Variation Aware Low Power Systems
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5766061
The demand for richer multimedia services, multifunctional portable devices and high data rates can only been visioned due to the improvement in semiconductor technology. Unfortunately, sub-90 nm process nodes uncover the nanometer Pandora-box exposing the barriers of technology scaling-parameter variations, that threaten the correct operation of circuits, and increased energy consumption, that limits the operational lifetime of today's systems. The contradictory design requirements for low-power and system robustness, is one of the most challenging design problems of today. The design efforts are further complicated due to the heterogeneous types of designs (logic, memory, mixed-signal) that are included in today's complex systems and are characterized by different design requirements. This paper presents an overview of techniques at various levels of design abstraction that lead to low power and variation aware logic, memory and mixed-signal circuits and can potentially assist in meeting the strict power b
-----------------------------------------------------------------------------------------------------------------
Mitra, S.;  Brelsford, K.;  Kim, Y. M.;  Lee, H.-H. K.;  Li, Y., Robust System Design to Overcome CMOS Reliability Challenges
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5751208
Today's mainstream electronic systems typically assume that transistors and interconnects operate correctly over their useful lifetime. With enormous complexity and significantly increased vulnerability to failures compared to the past, future system designs cannot rely on such assumptions. For coming generations of silicon technologies, several causes of hardware reliability failures, largely benign in the past, are becoming significant at the system level. Robust system design is essential to ensure that future systems perform correctly despite rising complexity and increasing disturbances. This paper describes three techniques that can enable a sea change in robust system design through cost-effective tolerance and prediction of failures in hardware during system operation: 1) efficient soft error resilience; 2) circuit failure prediction; and 3) effective on-line self-test and diagnostics. The need for global optimization across multiple abstraction layers is also demonstrated.
-----------------------------------------------------------------------------------------------------------------
Seok, M.;  Chen, G.;  Hanson, S.;  Wieckowski, M.;  Blaauw, D.;  Sylvester, D., CAS-FEST 2010: Mitigating Variability in Near-Threshold Computing
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5762379
Near threshold computing has recently gained significant interest due to its potential to address the prohibitive increase of power consumption in a wide spectrum of modern VLSI circuits. This tutorial paper starts by reviewing the benefits and challenges of near threshold computing. We focus on the challenge of variability and discuss circuit and architecture solutions tailored to three different circuit fabrics: logic, memory, and clock distribution. Soft-edge clocking, body-biasing, mismatch-tolerant memories, asynchronous operation and low-skew clock networks are presented to mitigate variability in the near threshold ${V} _{rm DD}$ regime.
-----------------------------------------------------------------------------------------------------------------
Maricau, E.;  Gielen, G., Computer-Aided Analog Circuit Design for Reliability in Nanometer CMOS
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5762376
Integrated analog circuit design in nanometer CMOS technologies brings forth new and significant reliability challenges. Ever-increasing process variability effects and transistor wear-out phenomena such as BTI, hot carrier degradation and dielectric breakdown force designers to use large design margins and to increase the uncertainty on the circuit lifetime. To help designers to tackle these problems at design time (i.e., Design For Reliability, or DFR), accurate transistor aging models, efficient circuit reliability analysis methods and novel design techniques are needed. The paper overviews the current state of the art in DFR for analog circuits. The most important unreliability effects in nanometer CMOS technologies are reviewed and transistor aging models, intended for accurate circuit simulation, are described. Also, efficient methods for circuit reliability simulation and analysis are discussed. These methods can help designers to analyze their circuits and to identify weak spots. Finally, cost-effect
-----------------------------------------------------------------------------------------------------------------
Zhang, X.;  Mukadam, M. Y.;  Mukhopadhyay, I.;  Apsel, A. B., Process Compensation Loops for High Speed Ring Oscillators in Sub-Micron CMOS
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5756255
In this paper, we present two implementations of a closed-loop process compensation scheme for high speed ring oscillators-the comparator based and the switched capacitor based loops. We provide detailed discussion of the frequency accuracy, loop stability, and implementation cost for each design. More than 150 test chips from multiple wafer-runs in a 90 nm CMOS process verify that frequency accuracy of better than 2.6% can be achieved with the application of the proposed compensation loop. Moreover, by leveraging a low variation addition-based current source, we have demonstrated a fully-integrated 2.15 GHz ring oscillator with less than 4.6% frequency variation without external references or post fabrication calibration, which is 3.8 $times$ improvement in frequency accuracy over the baseline case. The same compensation scheme can also alleviate frequency drift caused by temperature.

JETCAS is published quarterly and solicits, with particular emphasis on emerging areas, special issues on topics that cover the entire scope of the IEEE Circuits and Systems (CAS) Society, namely the theory, analysis, modeling, design, automation, and implementation of electronic circuits and systems, spanning theoretical foundations, applications, and architectures for signal and information processing.

Sunday, 12 June 2011

First Graphene Integrated Circuit


IBM researchers have built the first IC based on a graphene transistor. It is another step toward overcoming the limits of silicon and a potential path to flexible electronics [read more at spectrum.ieee.org]

Thursday, 9 June 2011

Alternative semiconductor fabrication methods enable inexpensive, conformable consumer devices - Solid State Technology

Alternative semiconductor fabrication methods enable inexpensive, conformable consumer devices - Solid State Technology

Emerging technology and a developing infrastructure for printed electronics is enabling circuitry that is flexible, conformable, and inexpensive to mass-produce. FlexTech Alliance has identified, funded, and directed advanced development in the flexible and printed electronics infrastructure, paving the way for the practical manufacture of a variety of low-cost applications such as electronic packaging, ID tags, and wide-area lighting panels.

Printed electronics include a set of consumer markets where printed logic and memory will be required. The size and cost of fully printed systems is set to challenge silicon-based technologies in ultra-high-volume distributed applications. To address this issue, Norwegian firm ThinFilm Electronics produces rewritable memory tags manufactured using full roll-to-roll (R2R) printing. Printed non-volatile RAM (NVRAM), when combined with printed transistor elements, serves as the basis of a new generation of cheap, disposable, and highly ubiquitous electronic devices. The company is working with major toy and game companies and has established high-volume manufacturing to deliver millions of tags per month.

In other commercial development, a new method for fabricating printed semiconductors, developed by NthDegree Technologies, allows a standard high-speed printing press to print conductive ink on to paper, plastic, or other substrate materials. Printed semiconductors made with these inks reduce the cost of producing semiconductor-based devices while creating innovative conformable products. Wide-area lighting is currently being produced with this technology by means of a light-emitting diode (LED) "ink". This LED ink is being used to print area lighting that is converted into a flat panel to replace fluorescent tube fixtures.

These latest developments in printed electronics materials, tools and processes, including LED lighting and printed memory, will be discussed and demonstrated at the Extreme Electronics TechXpot session "Printed electronics: Beyond R&D to real-deal technologies," presented by the FlexTech Alliance at SEMICON West, July 14, 2011. For more information about FlexTech Alliance visit www.flextech.org.

Freescale's Su calls for improved EDA tools

Freescale's Su calls for improved EDA tools:

As more embedded devices are being connected to the "Internet of things" the design methodologies used in IC designs need to change accordingly for faster chip turnarounds.

Lisa Su, VP and general manager of FreescaleLisa Su, VP and general manager of Freescale"Some 7 billion devices will be connected to the Internet in this era from 2006 to 2020," said Lisa Su, vice president and general manager of Freescale Semiconductor Inc's networking and multimedia group. "And mobile traffic is doubling every year through 2015."

Su delivered the Tuesday (June 7) keynote here at the Design Automation Conference, whose organizers have placed embedded systems and software squarely in the apex of DAC with dedicated exhibit areas on the show floor.

While only 15 exhibitors specifically identified themselves as embedded hardware/software providers out of a total of 200, the technical program was loaded with embedded presentations and Su's keynote was clearly aimed at showing that at least Freescale understands that it is operating in a new space for them, the embedded world.

"The embedded era is defined by standards-based hardware and software, is open source, and aimed numerous markets, including health, safety, energy, transportation, communications, entertainment, automation, and, of course, cloud computing," said Su.

Su quoted statistics that the monthly mobile traffic will increase tenfold from today's 0.6 exabytes to 6.3 exabytes by 2015. "The resultant heterogeneous networks, together with the increasing needs of the ‘connected' car, offer many opportunities to semiconductor companies like us," said Su.

The many-core paradigm of the expected SOC technology transition poses a few challenges, according to Su.

Among these are scalability as the number of cores per processor generation will double. Also there will be system tradeoffs to consider between cores versus using hardware acceleration, as well cluster optimization among cores, caches, local vs. global resource sharing. And an increasing amount of high-speed mixed-signal I/O will place strain on expected quality of service metrics.

read more...

Wednesday, 8 June 2011

Postdoc Position in Thin Films (Thun, CH)

Empa is the interdisciplinary research and services institution for material sciences and technology development of the ETH Domain. Laboratory for Mechanics of Materials and Nanostructures at Empa's location in Thun, CH, is offering an Academia / Industry Postdoc Position in Thin Films

Submit your application online and upload all documents through this webpage by June 30, 2011:
http://internet1.refline.ch/673276/0190/++publications++/1/index.html

Additional information can be obtained from the EMPA website and by contacting Dr. Johann Michler.

Tuesday, 7 June 2011

IEDM'2011 Abstract Submission Site is Now Open (Deadline: June 24, 2011)

IEDM Abstract Submission Site is Now Open - Abstract Submission
Deadline:   June 24, 2011

2011 IEEE International Electron Devices Meeting
The Annual Technical Meeting of the Electron Devices Society will be held at the
Washington Hilton, Washington, DC USA  - December 5-7, 2011

To view the IEDM Call for Papers and instructions for submitting an abstract to
the conference, visit:      http://www.ieee-iedm.org

IEEE International Electron Devices Meeting (IEDM) is the world’s pre-eminent
forum for reporting technological breakthroughs in the areas of semiconductor
and electronic device technology, design, manufacturing, physics, and modeling. 
IEDM is the flagship conference for nanometer-scale CMOS transistor technology,
advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale
devices and phenomenology, optoelectronics, devices for power and energy
harvesting, high-speed devices, as well as process technology and device
modeling and simulation.  

Starting this year (2011) there is an increased emphasis on circuit and device
interaction.  With ever increasing transistor count, nanometer design rules and
layout restrictions, circuit-device interaction is becoming critical to
providing viable technology solutions. This new emphasis includes
technology/circuit co-optimization, power/performance/area analyses, design for
manufacturing and process control, as well as CMOS platform technology and
scaling.

INCREASED PARTICIPATION IN THE FOLLOWING AREAS IS SOUGHT: 
 * Circuit-device interaction 
 * Energy harvesting
 * Biomedical devices
 * Power devices

Information about IEDM can be found at: http://www.ieee-iedm.org 
Twitter: http://twitter.com/ieee_iedm 
Facebook: http://www.facebook.com/pages/IEDM/131119756449 

MEETING HIGHLIGHTS 
 * New subcommittees (Circuit-Device Interaction and Nano Device Technology)
 * New for 2011:  90 Minute Tutorial Sessions on Emerging Topics, Saturday
afternoon, December 3
 * Three plenary presentations by prominent experts 
 * Invited papers on all aspects of advanced devices and technologies.
 * An Emerging Technology session. 
 * Two evening Panel discussions.
 * Presentation of IEEE/EDS awards. 
 * IEDM Luncheon presentation will be held on Tuesday, December 6.
 * Two short courses will be held on Sunday, December 4.

Further Information - All questions or inquiries for further information
regarding this meeting should be directed to the Conference Office at:

19803 Laurel Valley Place
Montgomery Village, MD 20886 USA
Tel: 301-527-0900, ext. 2
Email: iedm@his.com 
Local European Contact 

Stefan De Gendt, IMEC, Belgium
Local Asian Contact 
Norikatsu Takaura, LEAP, Japan
2011 Conference Chair 
Kazunari Ishimaru, Toshiba, Japan
Technical Program Chair 
Veena Misra, North Carolina State University, USA

If you know of any colleagues who may have a paper to contribute and have not
received this notice, please bring it to their attention.

Friday, 3 June 2011

Course on Statistical CMOS Variability and Reliability, San Jose CA, June 13th and 14th

Professor Asen Asenov, CEO of Gold Standard Simulations, will be delivering a comprehensive course (see the flyer) on variability and reliability issues and their impact on modern CMOS devices and design.

The course topics include, Variability classification,Sources of statistical variability, Simulation of statistical variability, Variability trends in conventional and novel MOSFETs, Random telegraph noise statistics, Statistical aspects of reliability, Statistical compact model strategies and Statistical circuit simulation. At this event there will also be a special lecture on Variability in FinFET devices.

For more information please visit: http://www.goldstandardsimulations.com/courses/ or get in touch with them at courses(at)goldstandardsimulations.com.

Thursday, 2 June 2011

Papers in Solid-State Electronics Volume 62, Issue 1, (August 2011)

A computationally efficient compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates   Original Research Article

Pages 31-39
Darsen D. Lu, Mohan V. Dunga, Chung-Hsun Lin, Ali M. Niknejad, Chenming Hu

Research highlights

► A computationally efficient approximation for surface potential in FDSOI MOSFETs is developed. ► IV and CV models for FDSOI MOSFETs are derived without making the charge sheet approximation. ► The core model and non-ideal effect expressions are implemented in Verilog-A language. ► The model is symmetric with respect to Vds = 0 and continuous in all regions of operation.


 An effective thermal circuit model for electro-thermal simulation of SOI analog circuits   Original Research Article

Pages 48-61
Ming-C. Cheng, Kun Zhang

Highlights

► A thermal circuit model is developed for SOI analog circuits. ► The model integrates a device thermal circuit with interconnect thermal networks. ► The device thermal circuit accounts for non-isothermal effects in SOI devices. ► Thermal networks for cross-coupled and parallel coupled wires are developed. ► The model is coupled with BSIMSOI for electro-thermal simulation of SOI circuits.



MOSFET modeling for design of ultra-high performance infrared CMOS imagers working at cryogenic temperatures: Case of an analog/digital 0.18 μm CMOS process   Original Research Article

Pages 115-122
P. Martin, A.S. Royet, F. Guellec, G. Ghibaudo

Research highlights

► Specific physical effects are observed in a cooled (77–200 K) 0.18 μm CMOS process. ► These effects are described and modeled for design of cryogenic IR CMOS imagers. ► Data on low frequency noise and transistor matching in MOSFET are also presented.



 Physics-based compact model for ultra-scaled FinFETs   Original Research Article

Pages 165-173
Ashkhen Yesayan, Fabien Prégaldiny, Nicolas Chevillon, Christophe Lallement, Jean-Michel Sallese

Highlights

► We propose a physical and explicit compact model for lightly doped FinFETs. ► This design-oriented model is valid for a large range of silicon Fin widths/lengths. ► It describes well the drain current, small signal parameters and capacitances. ► It takes into account all short-channel effects and quantum mechanical effects. ► This compact model needs a very few number of electrical parameters (4).



Three-dimensional analytic modelling of front and back gate threshold voltages for small geometry fully depleted SOI MOSFET’s   Original Research Article

Pages 174-184
Krishna Meel, R. Gopal, Deepak Bhatnagar

Highlights

► New 3-D front (back) gate threshold voltage models of FD-SOI MOSFETs are reported. ► Models solve 3-D Poisson’s equation using Green’s function as a tool. ► 3-D threshold voltage models include side wall, source/drain and back gate effects. ► Front and back gate charge coupling is incorporated in both the threshold voltages. ► Compact models of threshold voltages are amenable to circuit CAD tool.



Mobility analysis of surface roughness scattering in FinFET devices   Original Research Article

Pages 195-201
Jae Woo Lee, Doyoung Jang, Mireille Mouis, Gyu Tae Kim, Thomas Chiarella, Thomas Hoffmann, Gérard Ghibaudo

Highlights

► Mobility analysis of the surface roughness scattering along the different interfaces of FinFET devices. ► The sidewall and top surface drain current components were estimated from the total drain currents of different fin width conditions. ► The contribution of the surface roughness scattering was analysed and that on sidewalls was about three times stronger than on top surface for n-channel FinFETs.

Wednesday, 1 June 2011

[mos-ak] C4P MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Helsinki on Sept.16 2011

C4P MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Helsinki on Sept.16 2011
http://www.mos-ak.org/helsinki/

Together with the Organizing Committee and Extended MOS-AK/GSA TPC
Committee, we have pleasure to invite to the MOS-AK/GSA Workshop in
Helsinki on Sept.16 2011 with special panel: 40th Anniversary of SPICE
(panelists tentative alphabetic list):
* Narain D. Arora, Siltera, USA
* Christian Enz, CSEM, CH
* Andrei Vladimirescu, EECS, Berkeley
* Andreas Wild, ENIAC - JU, EU
and MOS-AK/GSA Transistor Level IC Design Challenge Opening

The MOS-AK/GSA Workshop is HiTech forum to discuss the frontiers of
the electron devices modeling with emphasis on simulation-aware
models. Original papers presenting new developments and advances in
the compact/spice modeling and its Verilog-A standardization are
solicited. The main topics of the workshop are: (but are not limited
to):
* Compact Modeling (CM) of the electron devices
* VHDL-AMS/Verilog-A for CM standardization
* New CM techniques and extraction software
* CM of passive, active, sensors and actuators
* Emerging devices, CMOS and SOI-based memory cells
* Microwave, RF device modeling, high voltage device modeling
* Transistor Level IC support
* Nanoscale CMOS devices and circuits
* Reliability and thermal management of electron devices
* Technology R&D, DFY, DFT and IC designs
* Foundry/Fabless interface strategies

The terms of participation:
Authors are asked to submit a short (~200words) abstract using on-line
submission form by JUNE 30 http://www.mos-ak.org/helsinki/abstracts.php

Intending authors should also note the following deadlines:
* Announcement and Call for Papers - May 2011
* on-line abstract submission deadline - June 30, 2011
* Final Workshop Program - August 2011
* MOS-AK/GSA Workshop - Sept. 16, 2011

On-line workshop registration: http://www.essderc2011.org/registration.php
Further details and updates: http://www.mos-ak.org/helsinki
Email contact: helsinki@mos-ak.org

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