Sunday, 30 May 2010

NHK Improves Resolution of Organic TFT-driven OLED Panel

NHK Science & Technology Research Laboratories (STRL) exhibited a flexible OLED panel driven by organic TFTs at OpenHouse 2010, which took place from May 27 to 30, 2010, in Tokyo [more]

Thursday, 27 May 2010

[mos-ak] C4P MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Seville on Sept. 17, 2010


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C4P MOS-AK/GSA ESSDERC/ESSCIRC Workshop:  http://www.mos-ak.org/seville/
"Frontiers of the Compact Modeling for Advanced Analog/RF Applications"

The MOS-AK/GSA Workshop in Seville will be organized as an integral
part of the ESSDERC/ESSCIRC Conference. The MOS-AK/GSA Workshop is
HiTech forum to discuss the frontiers of the electron devices modeling
with emphasis on simulation-aware models. Original papers presenting
new developments and advances in the compact/spice modeling and its
Verilog-A standardization are solicited. Suggested topics include (but
are not limited to):
   * Compact Modeling (CM) of the electron devices
   * Verilog-A language for CM standardization
   * New CM techniques and extraction software
   * CM of passive, active, sensors and actuators
   * Emerging Devices, CMOS and SOI-based memory cells
   * Microwave, RF device modeling, high voltage device modeling
   * Nanoscale CMOS devices and circuits
   * Technology R&D, DFY, DFT and IC Designs
   * Foundry/Fabless Interface Strategies

On-line abstract submission is open with the deadline on July 15, 2010.

Further details and updates: http://www.mos-ak.org/seville/

==========================================================
* Wroclaw: June 24-26 www.mixdes.org/Special_sessions.htm
* Tarragona: June.31-July.1  http://www.compactmodelling.eu/tc_programme.php
* Seville: Sept. 17  http://www.mos-ak.org/seville/
* California: Dec'2010 http://www.mos-ak.org/
==========================================================
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Wednesday, 26 May 2010

IEEE papers in May 2010

Why the Universal Mobility Is Not

Cristoloveanu, S.  Rodriguez, N.  Gamiz, F. 
Digital Object Identifier : 10.1109/TED.2010.2046109
Examples taken from ultrathin silicon-on-insulator (SOI) transistors tend to contradict the universality of mobility-field dependence. We revisit the meaning of the effective field concept and its implications on the universal mobility curve (UMC). Poisson–Schroedinger simulations point out the inappropriateness of the standard definitions of effective field when dealing with SOI or double-gate devices. Different carrier distributions can lead to the same value of the effective fie... Read More »

Compact and Distributed Modeling of Cryogenic Bulk MOSFET Operation

Akturk, A.  Holloway, M.  Potbhare, S.  Gundlach, D.  Li, B.  Goldsman, N.  Peckerar, M.  Cheung, K. P. 
Digital Object Identifier : 10.1109/TED.2010.2046458

We have developed compact and physics-based distributed numerical models for cryogenic bulk MOSFET operation down to 20 K to advance simulation and first-pass design of device and circuit operation at low temperatures. To achieve this, we measured and simulated temperature-dependent current–voltage characteristics of 0.16- and 0.18-$muhbox{m}$ bulk MOSFETs. Our measurements indicate that these MOSFETs supply approxim... Read More »


Compact Modeling of Experimental n- and p-Channel FinFETs

Song, J.  Yuan, Y.  Yu, B.  Xiong, W.  Taur, Y. 
Digital Object Identifier : 10.1109/TED.2010.2047067

The analytic potential model for symmetric double-gate MOSFETs is verified and calibrated with experimental n- and p-channel FinFET data over a wide range of gate lengths and bias regions. Quantum mechanical effects are incorporated in the model to reproduce the measured $C$$V$ characteristics. The long-channel mobility consists of both a phonon scat... Read More »

Compact Modeling of a Magnetic Tunnel Junction—Part I: Dynamic Magnetization Model

Kammerer, J.-B.  Madec, M.  Hébrard, L. 
Digital Object Identifier : 10.1109/TED.2010.2047070

The potential application range of spintronic devices is wide. However, few works were carried out in the field of compact modeling of such devices. The lack of compact models dramatically increases the design complexity of circuits using spintronic devices. In this paper, focus is made on magnetic tunnel junctions (MTJs). It is presented in a set of two papers: the first part deals with the magnetic aspects of the MTJ, whereas the second one covers the electrical aspects. In this part, a... Read More »



Compact Modeling of a Magnetic Tunnel Junction—Part II: Tunneling Current Model

Madec, M.  Kammerer, J.-B.  Hébrard, L. 
Digital Object Identifier : 10.1109/TED.2010.2047071

The potential application range of spintronic devices is wide. However, a few works were carried out in the field of compact modeling of such devices. The lack of compact models dramatically increases the design complexity of circuits using spintronic devices. In this paper, focus is made on magnetic tunnel junctions (MTJs). It is presented in a set of two papers: The first part deals with the magnetic aspects of the MTJ, whereas the second one covers the electrical aspects. In this part,... Read More »



Compact Modeling of LDMOS Transistors for Extreme Environment Analog Circuit Design

Kashyap, A. S.  Mantooth, H. A.  Vo, T. A.  Mojarradi, M. 
Digital Object Identifier : 10.1109/TED.2010.2046073

The cryogenic characterization (93 K/$- hbox{180} ^{circ}hbox{C}$ to 300 K/27 $^{circ}hbox{C}$) and compact modeling of a high-voltage (HV) laterally diffused MOS (LDMOS) transistor that exhibits carrier freeze-out are presented in this paper. Unlike low-voltage MOS devices, it was observed that HVMOS structures experience freeze-out effects at much higher t... Read More »



Variability Analysis of TiN Metal-Gate FinFETs

Endo, K.  O'uchi, S.  Ishikawa, Y.  Liu, Y.  Matsukawa, T.  Sakamoto, K.  Tsukada, J.  Yamauchi, H.  Masahara, M. 
Digital Object Identifier : 10.1109/LED.2010.2047091

Variability of TiN FinFET performance is comprehensively studied. It is found that the variation of the $V_{rm th}$ in the FinFET occurs and the standard deviations of the $V_{rm th}$ of nMOS and pMOS FinFETs are almost the same. From the analytical results, it is found that the $V_{rm th}$ var... Read More »

Transistor mismatch in 32 nm high-k metal-gate process



 

Extraction Technique of Trap Densities in Thin Films and at Insulator Interfaces of Thin-Film Transistors

Kimura, M. 
Digital Object Identifier : 10.1109/LED.2010.2045221

We have developed an extraction technique of trap densities in thin films and at insulator interfaces of thin-film transistors (TFTs). These trap densities can be extracted and separated from capacitance–voltage and current–voltage characteristics by numerically calculating $Q = CV$ , Poisson equation, carrier density equations, and Gauss' law. The outstanding advantages are intuitive understandability and a s... Read More »









Tuesday, 18 May 2010

Some papers (May 2010) I've found interesting...

Substrate Noise Coupling Mechanisms in Lightly Doped CMOS Transistors

Bronckers, S.;   Van der Plas, G.;   Vandersteen, G.;   Rolain, Y.;  
Interuniversity Microelectronics Centre (IMEC), Leuven, Belgium 
This paper appears in: Instrumentation and Measurement, IEEE Transactions on
Issue Date: June 2010
Volume:
59 Issue:6
On page(s): 1727 - 1733
ISSN: 0018-9456
Digital Object Identifier: 10.1109/TIM.2009.2024370 
Date of Publication: 03 May 2010
Date of Current Version: 10 May 2010

Substrate noise issues are a showstopper for the smooth integration of analog and digital circuitries on the same die. For the designer, it is not known how substrate noise couples into the transistors of the analog circuitry. This paper reveals the dominant coupling mechanisms with simulations and the corresponding measurements in a 0.13-$muhbox{m}$ triple-well common-source complementary metal–oxide–semiconductor (CMOS) transistor integrated on a lightly doped substrate. Substrate noise couples in either the ground or the bulk of the transistor. It is demonstrated that the importance of the coupling mechanisms depends on the resistance of the ground interconnect. For the technology node used, measurements show that substrate noise isolation is optimal for a ground resistance of 0.8 $Omega$.


Thermal shot noise in top-gated single carbon nanotube field effect transistors

Chaste, J.;   Pallecchi, E.;   Morfin, P.;   Feve, G.;   Kontos, T.;   Berroir, J.-M.;   Hakonen, P.;   Placais, B.;  
Laboratoire Pierre Aigrain, Ecole Normale Supérieure, CNRS (UMR 8551), Université P. et M. Curie, Université D. Diderot, 24, rue Lhomond, 75231 Paris Cedex 05, France 
This paper appears in: Applied Physics Letters
Issue Date: May 2010
Volume:
96 Issue:19
On page(s): 192103 - 192103-3
ISSN: 0003-6951
Digital Object Identifier: 10.1063/1.3425889 
Date of Current Version: 13 May 2010


The high-frequency transconductance and current noise of top-gated single carbon nanotube transistors have been measured and used to investigate hot electron effects in one-dimensional transistors. Results are in good agreement with a theory of one-dimensional nanotransistor. In particular the prediction of a large transconductance correction to the Johnson–Nyquist thermal noise formula is confirmed experimentally. Experiment shows that nanotube transistors can be used as fast charge detectors for quantum coherent electronics with a resolution of
13 μe/
 Hz

in the 0.2–0.8 GHz band. 

Dielectric constants of atomically thin silicon channels with double gate

Kageshima, Hiroyuki;   Fujiwara, Akira;  
NTT Basic Research Laboratories, NTT Corporation, 3-1 Morinosato-Wakamiya, Atsugi, Kanagawa 243-0198, Japan 
This paper appears in: Applied Physics Letters
Issue Date: May 2010
Volume: 96 Issue:19
On page(s): 193102 - 193102-3
ISSN: 0003-6951
Digital Object Identifier: 10.1063/1.3427364 
Date of Current Version: 13 May 2010
Dielectric constants of Si (111) nanofilms with the double gate are studied in the full inversion regime by using the first-principles calculation. The calculations show that the dielectric constants are significantly smaller than that of the bulk. Further, the dielectric constants depend on the conduction type as well as on the film thickness. They also oscillate with a 2-bilayer-thickness for the p-channel case as the film thickness decreases. The suppressed dielectric constants are found in the channel center as well as in the channel surface. These findings open the way to artificial control of the dielectric constant in semiconductor nanostructures.
 

Charge carrier densities in chemically doped organic semiconductors verified by two independent techniques

Lehnhardt, M.;   Hamwi, S.;   Hoping, M.;   Reinker, J.;   Riedl, T.;   Kowalsky, W.;  
Institute for High-Frequency Technology, Technical University of Braunschweig, Schleinitzstr. 22, D-38106 Braunschweig, Germany 
This paper appears in: Applied Physics Letters
Issue Date: May 2010
Volume: 96 Issue:19
On page(s): 193301 - 193301-3
ISSN: 0003-6951
Digital Object Identifier: 10.1063/1.3427416 
Date of Current Version: 13 May 2010

The charge carrier density of the p-type doped organic semiconductor 2,7-bis(9-carbazolyl)-9,9-spirobifluorene is determined for varied doping concentrations. As p-type dopant molybdenum trioxide is used. We determine the carrier density by measuring the polaron induced optical absorption and by a capacitance-voltage analysis. We show that both results are in excellent agreement. An almost linear dependence of the charge carrier density on the doping concentration is observed. Carrier densities on the order of 1018 cm-3 at a dopant concentration of 1 mol % can be achieved. Overall, a low doping efficiency on the order of 2%–4.5% is evidenced.


The effect of traps on the performance of graphene field-effect transistors

Zhu, J.;   Jhaveri, R.;   Woo, J. C. S.;  
Department of Electrical Engineering, University of California–Los Angeles, Los Angeles, California 90095-1594, USA 
This paper appears in: Applied Physics Letters
Issue Date: May 2010
Volume:
96 Issue:19
On page(s): 193503 - 193503-3
ISSN: 0003-6951
Digital Object Identifier: 10.1063/1.3428785 
Date of Current Version: 13 May 2010

This paper studies the performance degradation of graphene field-effect transistors due to the presence of traps. The mobile charge modulation by gate voltage is degraded because of immobile trapped charges. As a result the current is reduced and the on/off ratio is decreased. Extracted mobility using transconductance method is shown to be underestimated considerably due to the effect of traps.
 

Tuesday, 11 May 2010

Training Course on Compact Modeling: Registration Open

The first edition of the Training Courses on Compact Modeling (TCCM) will be held in Tarragona, Catalonia, Spain) on June 30-July 1, in coordination with two other events partially or totally related to compact modeling: the 8th Graduate Student Meeting on Electronic Engineering (June 28-29) and the 3rd International Workshop on Compact Thin Film Transistor Modeling (July 2).

The Training Course will consist on 12 lectures addressing relevant topics in the compact modeling of advanced electron devices. In particular, emphasis will be given on MOSFETs (bulk, SOI, Multi-Gate and High Voltage MOS structures) and HEMTs.

The Training Courses on Compact Modeling are sponsored by the European Union FP7 “COMON” IAPP Project, the European Union FP7 NANOSIL Network of Excellence and the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee.


REGISTRATION IS OPEN

It is cheap and includes two lunches and one gala dinner. The advanced registration fee will be 100 Euro for students and 130 Euro for non-students. After June 13, the registration fee is 150 Euro for students and 180 Euro for non-students. Members of the teams participating in the COMON project are exempted from paying the fee, and members of teams participating in NANOSIL pay a reduced fee.

The lectures and topics of their lectures will be the following:


1. Tibor Grasser (TU-Wien, Austria) - Transport modeling

2. Tor A Fjeldly (UniK, Norway) - Analytical 2D and 3D electrostatic modeling

3. Jamal Deen (McMaster University, Canada) - Noise modeling

4. Benjamin Iñiguez (URV, Spain) - Analytical small-signal modeling

5. Ilcho Angelov (Chalmers University, Sweden) - High frequency device modeling

6. Renaud Gillon (On Semiconductor, Belgium) - Electro-thermal and reliability modeling

7. Sorin Cristoloveanu (MINATEC and LETI, France) - Electrical characterization of SOI and Multi-Gate MOSFETs

8. Asen Asenov (University of Glasgow) - Statistical variability and corresponding compact model strategies

9. Kiyoh Itoh (Hitachi, Japan) - "Variability-conscious Circuit Designs for Low-voltage Nano-scale CMOS LSIs"

10. Wladek Grabinski - "GNU/Open Source CAD Tools for Verilog-A Compact Model Standardization"

11. Antonio Cerdeira (Cinvestav, Mexico) - "DC Parameter Extraction"

12. Massimo Poncino (Politecnico di Torino, Italia) - "Leakage power modeling for the reduction of power consumption in CMOS ICs"

The final programme, with the timetable, is already available!

Saturday, 8 May 2010

May 7, 1952: The Integrated Circuit …



1952: British radar engineer Geoffrey Dummer introduces the concept of the integrated circuit at a tech conference in the United States. The world is about to change. Read more... by www.wired.com

Organic Transistor Could Outshine OLEDs



”The light-emitting transistor is a remarkably versatile device architecture,” says Alan Heeger, a physics professor at the University of California, Santa Barbara. Heeger’s lab developed an OLET inverter circuit earlier, but its quantum efficiency was much lower. He called the 5 percent external quantum efficiency ”remarkable,” because it suggests that nearly 100 percent of the carriers in the emissive layer are emitting photons. ”If that is indeed true,” Heeger says, ”they have made an important step forward.”

Friday, 7 May 2010

3rd International Workshop on Copact TFT Modeling for Circuit Simulation: Deadline Extended

The 3rd International Workshop on Compact Thin-Film Transistor Modeling for Circuit Simulation (C-TFT) will be held in Tarragona on July 2 2010.

Deadline for abstract submission has been extended:

- Deadline for abstract submission: May 19, 2010
- Notification of acceptance: May 26, 2010
- Camera-ready version: Jun 18, 2010

The C-TFT Workshop will provide a forum for discussions and current practices on compact TFT modeling. The workshop is sponsored by the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee and the University College London.

Topics:
A partial list of the areas of interest includes:

- Physics of TFTs and operating principles
- Compact TFT device models for circuit simulation
- Model implementation and circuit analysis techniques
- Model parameter extraction techniques
- Applications of compact TFT models in emerging products
- Compact models for interconnects in active matrix flat panels

Prospective authors are invited to submit an abstract of up to 500-word to: nae.bogden@urv.cat



This event will be held in coordination with the Training Courses on Compact Modeling (June 30-July 1) and the Graduate Student Meeting on Electronic Engineering (June 28-29).

Tarragona is located in the south of Catalonia, in the northeast corner of the Iberian Peninsula. Tarraco (the Roman name for Tarragona) was one of the most important cities in the Roman Empire. On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tarraco a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.

Wednesday, 5 May 2010

EPFL MicroNano Fabrication Annual Review Meeting

The Networking Event organized by the EPFL Center of MicroNanoTechnology (CMi)

Date: Tuesday May 18th, 2010
Time: 09h30 - 17h00
Place: EPFL Lausanne, Salle Polyvalente, Centre Est, CE 1 515

Program :
The presented topics include:
  • Biomedical Applications (Microfluidics, Cellular-Manipulation, Microelectrode Arrays, Molecules Detection, BioMicroNanoSystems, ...)
  • Optics (Nanophotonics, Optomechanics, Optofluidics, MOEMS, ...)
  • Micro and Nanoelectronics (Nanowires, High-Q Resonators, RF MEMS and Switches, 3D integration, CMOS, ...)
  • Nanostructure Physics (III/V Devices, Nanotubes, Nanowires, Nanomechanics, ...)
  • Material Sciences (Graphene, Polymers, Piezoelectric Ceramics, Photovoltaic Materials, Micro Fuel Cells, ...)
  • MEMS, NEMS (Motors, Tweezers, Sensors and Actuators, Micro and Nanomechanics, ...)
  • Micro and Nanofabrication Technologies (Self-Assembly, EBEAM Lithography, Dry Etching, Thin Films, Photolithography, FIB, CMP, ...)
  • Packaging and Assembly
Registration is required by sending an email to: claudia.dagostino@epfl.ch

Tuesday, 4 May 2010

Compact Modeling: Principles, Techniques and Applications

Gildenblat, Gennady (Ed.)
1st Edition., 2010, 545 p., Hardcover
ISBN: 978-90-481-8613-6
Erscheinungstermin: Juli 2010







Monday, 3 May 2010

[mos-ak] MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Seville: 1st announcement

MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Seville
*** 1st announcement ***

Date: September 17, 2010
Venue: Barceló Hotel Renacimiento

Co-Located With:
* 40th European Solid-State Device Research Conference (ESSDERC):
http://www.essderc2010.org
* 36th European Solid-State Circuits Conference (ESSCIRC) :
http://www.esscirc2010.org
* CMC Meeting (Q3 Event in Madrid): http://www.geia.org/index.asp?bid=597

More MOS-AK/GSA information and updates: http://www.mos-ak.org/seville/

Extended MOS-AK/GSA Committee:
===========================
http://www.mos-ak.org/committee.html
===========================
MOS-AK/GSA North America:
Chair: Pekka Ojala, Exar Corporation
Co-Chair: Geoffrey Coram, Analog Devices
Co-Chair: Prof. Jamal Deen, U.McMaster

MOS-AK/GSA South America:
Chair: Prof. Gilson I Wirth; UFRGS; Brazil
Co-Chair: Prof. Carlos Galup-Montor, UFSC; Brazil

MOS-AK/GSA Europe:
Chair: Ehrenfried Seebacher, austriamicrosystems AG
Co-Chair: Sebastian Schmidt, XFab
Co-Chair: Prof. Benjamin Iniguez, URV

MOS-AK/GSA Asia/Pacific:
Chair: Goichi Yokomizo, STARC, Japan
Co-Chair: Sadayuki Yoshitomi, Toshiba, Japan
Co-Chair: Xing Zhou, NTU, Singapore
===========================

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Sunday, 2 May 2010

Thoughts on Directions for Silicon Technology Development as we Approach the End of CMOS Scaling

Speaker: Dr. Tak H. Ning, IBM and IEEE Fellow, and co-author of the Taur & Ning textbook now in its second edition.
Date: TUESDAY, May 11, 2010; Time: 6:00 PM - Pizza, 6:15 PM – Lecture; Cost: Free
Location: National Semiconductor, Building E1, Conference Center, 2900 Semiconductor Drive, Santa Clara, CA 95051
Web link: http://www.ewh.ieee.org/r6/scv/eds/
Contact: Sandeep Bahl