Monday, 31 December 2007

Happy new year!

With our best wishes, we hope the new year 2008 will bring happiness and joy to you and all your loved ones.

Benjamin and Rodrigo

Thursday, 20 December 2007

2008 IEEE Compound Semiconductor IC Symposium

The 2008 IEEE Compound Semiconductor IC Symposium (CSICS 20008)
will take place in Monterey (in the Portola Plaza Hotel) in October 12-15 2008.

CSICS is the major conference in Compound Semiconductor technologies integrated circuits. The scope of the conference includes all topics related to the fabrication, design, applications, testing, packaging and reliability of compound semiconductor devices and circuits. All compound semiconductor technologies are addressed: GaAs, GaN, SiGe, InP,...

The deadline for electronic receipt of abstracts is May 12 2008.

Extended versions of selected papers will be published in a special issue of the IEEE Journal of Solid State Circuits.

Besides, CSICs 2008 will offer the popular primer course "Basics of GaAs, InP and SiGe RFICs".


And, last but not least, the Symposium offers the possibility to enjoy several days in the beautiful and picturesque city of Monterey, with its famous Monterey Bay Aquarium, wonderful beaches, the Monterey Bay harbor and hundreds of dining and entertainment options, including the famous Bubba Gump Shrimp restaurant!

Wednesday, 19 December 2007

Nanotube-Producing Bacteria

Two engineers at the University of California, Riverside are part of a team that has found semiconducting nanotubes produced by living bacteria – a discovery that could help in the creation of a new generation of nanoelectronic devices.

Have a look at the full story at Semiconductor Online, or have a look at the original press release.

Genus Shewanella. The nanotube filaments produced by biological means could point toward semiconductor manufacturing processes with a smaller energy and environmental footprint. Image credit: Hor-Gil Hur, GIST

Tuesday, 18 December 2007

A paper on IEEJ Transactions on Electrical and Electronic Engineering

In this month's issue (Volume 3, Issue 1, 2008), I've found an interesting paper from the HiSim people. Have a look at it:
A Gate-Current Model for Advanced MOSFET Technologies Implemented into HiSIM2
(Ryosuke Inagaki, Norio Sadachika, Dondee Navarro, Mitiko Miura-Mattausch, Yasuaki Inoue)

Tuesday, 11 December 2007

IEEE Staff Member Awarded

William F. Van Der Vort, executive director of the IEEE Electron Devices Society, received this year's Eric Herz Outstanding Staff Member Award.
The annual IEEE-sponsored award recognizes leadership and contributions to the success of the IEEE over a long period of time. Read on at http://bmsmail3.ieee.org:80/u/8823/40298008

Saturday, 8 December 2007

International Symposium on Flexible Electronics 2008

The first International Symposium on Flexible Electronics (ISFE 2008) will be held in Tarragona, Catalonia, Spain, on April 6-9 2008.

This new conference is sponsored by the Engineering Conferences International (ECI) Foundation, together with the Universitat Rovira i Virgili (URV, Tarragona, Spain)

The deadline for 300-word abstracts for oral presentations has been extended to December 17 2008.

Abstracts for posters can be sent until February 2008, but will not be published in the Book of Abstracts.

The invited speakers who have confirmed their participation are:

Prof. Michael S Shur (RPI, Troy, NY, USA)
Prof. Yue Kuo (Texas A&M University)
Prof. M. Jamal Deen (McMaster University, Hamilton, ON, Canada)
Prof. Takao Someya (Tokyo University, Japan)
Dr Warren Jackson (HP, Palo Alto, CA, USA)
Prof. William Eccleston (University of Liverpool, UK)
Dr Euan Smith (CDT, Cambridge, UK)
Dr Hagen Klauk (Max Planck Institute for Solid-State Physics, Stuttgart, Germany)

Sunday, 2 December 2007

MIXDES Special Session on Compact Modelling

Let me remind you about a special session on Compact Modelling which
will be held during the nearest MIXDES Conference, Poznan', June 19-21,
2008 (http://www.mixdes.org). Its main topic, i.e. "Compact Modeling and
Characterization of Nano CMOS Technologies" is very, very closely
related the COMON domain. I am sure, that Your participation would
enrich the session level and would be very helpful for COMON activity.

Papers in JAP

Nonequilibrium transport of charge carriers and transient electroluminescence in organic light-emitting diodes
V. R. Nikitenko and H. von Seggern
J. Appl. Phys. 102, 103708 (2007) (9 pages)
Abstract

Generation-recombination and thermal noise coupling in the drift-diffusion model
Fabio E. Zocchi
J. Appl. Phys. 102, 103712 (2007) (5 pages)
Abstract

Quantum conductance in single- and double-wall carbon nanotube networks
M. Baxendale, M. Melli, Z. Alemipour, I. Pollini, and T. J. S. Dennis
J. Appl. Phys. 102, 103721 (2007) (6 pages)
Abstract

Determination of trap distributions from current characteristics of pentacene field-effect transistors with surface modified gate oxide
Susanne Scheinert, Kurt P. Pernstich, Bertram Batlogg, and Gernot Paasch
J. Appl. Phys. 102, 104503 (2007) (8 pages)
Abstract

A numerical model for explaining the role of the interface morphology in composite solar cells
C. M. Martin, V. M. Burlakov, H. E. Assender, and D. A. R. Barkhouse
J. Appl. Phys. 102, 104506 (2007) (9 pages)
Abstract

Thursday, 29 November 2007

An industrial view on Compact Modelling

A quite interesting paper that came out in the 2006 ESSDERC, and has now been published in an special issue of the IEEE TED. It has been written by R. Woltjer, L. Tiemeijer and D. Klaassen,
from the Philips Research Labs., Eindhoven.
They review compact modelling from its beginnings, and explain two different examples (the PSP model, obiously, and a compact model for integrated inductors). It is quite interesting as a first (or second...) contact with this world.
By the way, the paper (An industrial view on Compact Modelling) is here.

MSM 2008

The 11th International Conference on Modeling and Simulation of Microsystems (MSM 2008) will be held in the Hynes Convention Center in Boston (Massachussets, USA) on June 1-5 2008, as part of the Nanotech 2008 Conference.

MSM is the main technical forum to present the latest research and development in design, modeling and simulation methods, tools and applications in the MEMS, microelectronic, semiconductor, sensor, materials and biotechnology fields. Process, device and circuit simulation is one of the topics explicitly mentioned. Semiconductors and Microelectronics is indicated as one of the application areas.

The Electronics and Microsystems suite of symposia at Nanotech 2008 has become a premier annual event in the Micro and Nano technologies arena. This Electronics and Microsystems suite of symposia is composed with the MEMS & NEMS, Sensors & Systems, Micro & Nano Fluidics symposia, andthe MSM conference The deadline for abstract submission is December 6 2007.

Selected proceedings papers in the Electronics and Microsystems Track (MEMS & NEMS, Sensors & Systems, Micro & Nano Fluidics symposia, and MSM conference) will be reviewed and invited into a Special Issue of the on-line magazine ‘Sensors & Transducers’ (S&T e-Digest).

WCM'08

The 2008 Workshop on Compact Modeling (WCM 2008) will be held in the Hynes Convention Center in Boston (Massachussets, USA) on June 1-5 2008, as part of the Nanotech 2008 Conference.

The Workshop on Compact Modeling (WCM) is one of the largest event devoted to the Compact Modeling field. WCM has become a very important open forum for discussion among experts in this field as well as feedback from technology developers, circuit designers, and EDA tool vendors.

The suggested topics include all important aspects of compact model development and application: intrinsic models, extrinsic/interconnec models, atom/quantum models, statistical models, and model extraction and interface.

A limited number of papers will be selected for oral presentations and the remaining accepted papers will be planned for poster presentations with oral briefing. The deadline for abstract submission is December 6 2007.

The Chairman of WCM is Professor Xing Zhou (from Nanyang Technological University, Singapore). He was the person who created WCM and has made this workshop very successful.

I think that it is a must for Compact Modeling researchers to attend WCM. Many of the last advances in this field are presented there.

IEEE TED and TNT Special Issue on Nanowire Electronics

IEEE Transactions on Electron Devices and IEEE Transactions on Nanotechnology have published a Call for Papers for a Joint Special Issue on Nanowire Electronics.

Suggested topics include Devices, Technology, Applications, Modeling and Quantum Simulations. Compact modeling for circuit design is explicitly mentioned as one of the topics.

The deadline for paper submission is April 30 2008, and the publication date will be November 2008.

Saturday, 10 November 2007

New papers (APL)

Some new interesting papers on this month issue of Applied Physics Letters (APL):

Threshold voltage stability of organic field-effect transistors for various chemical species in the insulator surface
Kouji Suemori, Sei Uemura, Manabu Yoshida, Satoshi Hoshino, Noriyuki Takada, Takehito Kodzasa, and Toshihide Kamata
Appl. Phys. Lett. 91, 192112 (2007) (3 pages)
Abstract

High performance n-channel thin-film transistors with an amorphous phase C60 film on plastic substrate
Jong H. Na, M. Kitamura, and Y. Arakawa
Appl. Phys. Lett. 91, 193501 (2007) (3 pages)
Abstract

The influence of visible light on transparent zinc tin oxide thin film transistors
P. Görrn, M. Lehnhardt, T. Riedl, and W. Kowalsky
Appl. Phys. Lett. 91, 193504 (2007) (3 pages)
Abstract

Flexible programmable logic gate using organic ferroelectric multilayer
Satoshi Horie, Kei Noda, Hirofumi Yamada, Kazumi Matsushige, Kenji Ishida, and Shuichiro Kuwajima
Appl. Phys. Lett. 91, 193506 (2007) (3 pages)
Abstract

Numerical modeling study of the unipolar accumulation transistor
Stephen J. Fonash, Md Mash-hud Iqbal, Florin Udrea, and Piero Migliorato
Appl. Phys. Lett. 91, 193508 (2007) (3 pages)
Abstract

Interface effects on the external quantum efficiency of organic bulk heterojunction photodetectors
Y. Kim, M. Ballarotto, D. Park, M. Du, W. Cao, C. H. Lee, W. N. Herman, and D. B. Romero
Appl. Phys. Lett. 91, 193510 (2007) (3 pages)
Abstract

Thursday, 8 November 2007

New online demo and tutorial from Mentor

ou're invited – Seminar: Reducing Verification Cycle Times with Calibre
Two new product demos/tutorials have been added to Mentor's online event library. Both events are available on-demand and you can attend one or both at your convenience.

»   Online Tutorial: Approaching Yield in the Nanometer Age
The Framework for an extensible DFM Methodology.

Overview:
As we dive deeper into the nanometer space, we must rethink the way we design. Tools, techniques, and methods that once worked without fail cannot hold up at the 65 and 45 nm depths, making it more challenging than ever to achieve
yield.

Not only are more DRC rules required, but the rules are becoming much more complex in light of more manufacturing issues. Yet advanced DRC is still not enough. We must redefine the sign-off process itself to include a spectrum of new methods that assess design quality. More of the responsibility for yield must shift to the designer, so the fabless model, where foundry information flows freely, increases in importance.

In the nanometer age, sign-off must include not only fundamental, rule-based physical verification and parasitic extraction, but also a set of automated technologies that help improve yield by enhancing the design itself.

What you will learn:
This tutorial goes into detail on these new technical challenges and solutions within both the business and historical context of the IC design and manufacturing process. It shows the importance of the fabless model as part of a more holistic DFM methodology, and includes demonstrations of what the new tools look like.

DFM Tools demonstrated:
  • Calibre YieldAnalyzer
  • Calibre YieldEnhancer
  • Calibre YieldServer
Register/Play Tutorial
 
»   Product Demo: Calibre LVS Integrated Design Debug Environment

Overview:
This online demo shows how IC designers can easily verify their designs throughout the entire IC design process, using Calibre LVS and the integrated design debug environment. We look at some typical LVS designs errors, and show the user how to easily identify these, fix them, and then validate that they are fixed correctly. The strong integration Calibre has into the Cadence Virtuoso design environment is shown as part of the design flow.

What you will learn:
  • How to easily track down IC design errors using Calibre LVS
  • How to identify the locations of these errors in your design environment
  • How Calibre interacts with the Cadence Virtuoso design creation environment
  • How Calibre LVS can improve your productivity by reducing your LVS debugging time
Tools demonstrated:
  • Calibre LVS to verify your IC design
  • Calibre RVE to visualize the results and identify them in the Cadence Virtuoso environment
  • Calibre Interactive as a launch platform to re-run your verification once the design has been fixed
Register/Play Demo
 
 

Mentor Graphics Corporation
Website: http://www.mentor.com/products/ic_nanometer_design
Email: DSM_info@mentor.com


Tuesday, 6 November 2007

IWCM'08

The 5th International Workshop on Compact Modeling (IWCM 2008) will be held in the Seoul (Korea) on January 21 2008. The venue will be the Korean Convention & Exhibition Centre (COEX) in Seoul

IWCM is an interesting forum to present and discuss the recent advances in compact modeling and simulation of semiconductor devices and integrated circuits. Actually IWCM is one of the few existing Workshops devoted mostly to compact modeling, and the only one who takes place in Asia.

IWCM is collocated with the 13th Asian and South Pacific Design Automation Conference (ASP-DAC'08).

The topics of IWCM are:
- Compact modeling for all kinds of devices
- Parameter extraction methodology and strategy
- Circuit simulation techniques

Abstracts should be submitted by November 2007.

The invited speakers will be: W. Fichtner (Synopsys, USA), M. Miura-Mattausch (Hiroshima University, Japan) and Y. J. Park (Seoul National University, Korea)


.

Sunday, 4 November 2007

Cadence Announces Academic Network To Promote Electronic Design Competency In Europe


San Jose, CA and Feldkirchen, Germany -- Cadence Design Systems, GmbH announced the formation of an academic network in Europe to promote the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence. This initiative will establish a knowledge network among selected European universities, research institutes, industry advisors and Cadence to facilitate the sharing of technology expertise in the areas of verification, design and implementation of microelectronic circuits.

Universities were selected with particular strengths and competencies in mind-- such as analog mixed-signal, radio frequency (RF), and low power design, all of which have been identified as key challenges for the coming years by the electronics industry. Under the initiative, Cadence will provide software, training and design methodology instruction to each of the institutions. Trained on the latest techniques with leading-edge software, the universities will then share their knowledge with other academic and research institutions. Students from these universities will graduate with an in-depth knowledge of how to tackle the pressing design issues that the industry is facing, learned on the most advanced design automation products available today.

So far three universities have joined the network in lead roles: The University of Heidelberg will lead high-level verification methodology; the Technical University of Ilmenau will concentrate on RF design methodology; and the Albert-Ludwigs-University of Freiburg will be the lead university for analog mixed-signal methodology. Planning to join the initiative shortly are the Polytechnic University of Bucharest, Romania, the University of Bristol, UK, and the University of Pavia in Italy.

"Our high standards in teaching and research have led Cadence to select us to be the lead university for analog mixed-signal methodology," said Prof. Dr.-Ing. Yiannos Manoli, head of the Microelectronics Group at IMTEK, University of Freiburg and Director of HSG-IMIT. "The increasing demand for highly skilled graduates in microelectronic design requires a solid and broad theoretical knowledge combined with a practical skill set in state-of-the-art techniques. Being part of this network will enable us to instruct our students using leading-edge technology."

Sean Redmond, vice president, EMEA for Cadence, said: "With the increase in development of complex industrial electronic systems, our customers are finding that they need engineers with broad technology competence. This network provides an exchange platform for the industry, academia and Cadence to stimulate the use of leading-edge technology at these universities. We are enthusiastic about this initiative and believe that the broad portfolio of Cadence solutions provides a perfect instrument to transfer up-to-date design methodology."

SOURCE: RF Globalnet, Cadence Design Systems, Inc.

Forward This Article To An Associate

Saturday, 3 November 2007

Another job for a Compact Modeling Specialist

Compact Model Engineer - Device Physics, C, Matlab, Compact Modeling
Category : Software, Hardware/ EDP
Role : Hardware Design Engineer
Company :
Alp Management Consultants Pvt. Ltd. | View all jobs for this company
Location :
Bangalore
Openings (15) Expires on : 30th Nov 2007



Note: denote mandatory requirements
Job Requirements
Experience :
3 - 6 Yrs
Education : Ph. D
Electrical, Electronics/ Telecommunications, Instrumentation, Physics
Job Description
Key Skills :
Device Physics, C, Matlab, Compact Modeling
Description : Job Description :

Develop compact models for advanced CMOS, mixed signal, and Radio Frequency technologies. Work closely with device design engineers to define parameter targets that correctly represent the technology goals and device data. Define and debug test programs to device current, capacitance, and S parameters. Use software such as ICCAP to extract parameters for BSIM4, HiCUM, MEXTRAM, or PSP models that optimally describe the device behavior for a single device. Modify those parameters to represent targeted device performance. Release models to circuit design engineers. Work closely with circuit designer engineers debugging circuit performance issues.

Desired Experience : 3+ Yrs

Required Skills :

Device Physics
Compact Modeling
C, SAS, and/or matlab
Problem solving
Communication, Teamwork, and Leadership

Please forward your updated resume and also refer your friend or colleague who are interested to change.

Email : vikas.s@alpconsultants.com
Tel : 011 - 46022609(D)

Tuesday, 30 October 2007

Jobs in compact modelling

More job offers: RF Magic and Kilopass... They are not as known as HP, but perhaps it is worth a look...

Urgent!!!! Job in Compact Modelling

The IHP - Innovations for High Performance Microelectronics

invites applications for a position in

Engineer for CMOS Compact Modelling and Technology Support
AZ 3102/07

The IHP consists of approximately 200 research staff, primarily in the area of wireless communications, including SiGe-based technologies, diagnostics, and materials research. We are working in a multidisciplinary environment, spanning materials, process technology, circuits, and systems. The IHP is housed in a state-of-the-art building 55 minutes from Berlin, with ultra-modern facilities. Our innovations are in worldwide demand.

We are seeking a candidate with a Master degree in Electrical Engineering or Physics in the field of CMOS compact modelling. The main tasks will be the characterization of advanced CMOS devices and extraction of SPICE models for IHP 0.25µm and 0.13µm technologies. Further he has to support statistical analysis of electrical test data.

The successful candidate will be highly motivated with good experimental, computing, and theoretical skills. Experience in semiconductor device physics and in one or more of the following fields would be an advantage: Compact modelling, Silicon IC technology, electrical parameter analysis.

The position offers a unique opportunity to work at the forefront of semiconductor technology in an upcoming new field. We offer a challenging, multinational environment, with excellent career prospects for highly motivated individuals. You will have the opportunity to establish an international reputation at the forefront of high tech.

The position will be filled as quickly as possible. Salary will be on the TV-L scale.

Please send your application letter/e-mail by October 31, 2007 including CV, copies of (scanned) certificates, and addresses of at least one referee to:

Dr. Christel Quick

IHP GmbH

Im Technologiepark 25

15236 Frankfurt (Oder)

Germany

Phone: +49 335 5625 330

Fax: +49 335 5625 666

Email: quick@ihp-microelectronics.com

For further information please contact:

Dr. Rene Scholz

IHP GmbH

Im Technologiepark 25

15236 Frankfurt (Oder)

Germany

Phone: +49 335 5625 647

Fax: +49 335 5625 327

E-mail: scholz@ihp-microelectronics.com

Monday, 29 October 2007

A Compact Model for OLEDs

An interesting paper in the last issue (91) of Applied Physics Letters from Ling Li, Gregor Meller, and Hans Kosina.
As they say: "The diffusion-controlled injection process in OLED is investigated and the concept of critical distance is proposed. A compact injection model applicable to OLED is formulated. This model is shown to fit the experimental data well and to explain the dependency of the injection current on the barrier height, the temperature, and the electric field. It was found that the field-dependent mobility plays an important role in the injection model at higher electric field."

Have a look here:

Diffusion-controlled charge injection model for organic light-emitting diodes
Ling Li, Gregor Meller, and Hans Kosina
Appl. Phys. Lett. 91, 172111 (2007) (3 pages)
Abstract

Wednesday, 24 October 2007

A paper on FinFET circuits

In this month's issue of the IEEE Trans. on CAD, there is a very interesting paper from K.Roy et al, who present some interesting techniques to deal with FinFETs to create circuits. Have a look here. The model they present to estimate the current is an alpha-law one, but I should think the idea is nice and could be developed further using more complex (I mean, exact...) models.

Tuesday, 23 October 2007

MIXDES'08

Let me draw Your attention to the annual International Conference Mixed Design of Integrated Circuits and Systems (http://www.mixdes.org/), which has been organized in Poland since 1994 by the Department of Microelectronics and Computer Science, Technical University of Łódź, Poland. For the last 8 years, special sessions on Compact Modeling have been organized as an event accompanying MIXDES conferences. They have become a well recognized forum of CM knowledge exchange. Since their beginning Wladek Grabinski has been their chairman and main organizer. This year, he is being assisted by Daniel Tomaszewski in the session organization.

The next edition of the MIXDES and of the special session on Compact Modeling will be held in Poznań, 19-21 June 2008. You are kindly invited to take part in this event which, I am sure, will enrich you with many satisfying experiences, including, why not, visiting the beautiful old quarter of Poznán, with the cathedral and the old market.

Friday, 19 October 2007

ITC'08

The 4th International TFT Conference (ITC'08) will take place in Chungwoonkwan, Kyung Hee University, in Seoul, Korea, on January 24-25 2008.

ITC is an annual conference which addresses all topics related to Thin Film Transistors (TFTs), from process to circuits, also including simulation and compact modeling.

Abstracts should be submitted not later than October 30 for evaluation.

A number of talks will be given by prestigeous invited speakers, such as P. Miglorato, G. Fortunato, E. Fortunato, T. Someya, H. Matsumura, Y. Uraoka, or Y. Kuo.

No doubt ITC 2008 will be a very interesting conference. Last year it was held in Rome and it was quite successful. Besides, a number of papers presented in ITC'07 were selected to be published in a Special Issue of Solid-State Electronics.

Monday, 8 October 2007

First International Symposium on Flexible Electronics (ISFE)

The First International Symposium on Flexible Electronics (ISFE) will be held in from 6-9 April 2008 in Tarragona (Catalonia, Spain). This conference will provide an opportunity to present and discuss recent advances in all topics related to flexible electronics, from the material to the circuit and system levels. The enormous increase of the applications of Flexible Electronics makes it necessary to create such a conference. The scientific program consists of invited and contributed presentations as well as one poster session.

I will be the Chairman of the ISFE Symposium. Prestigeous researchers from academia and industry are members of the Organizing and Technical Committees: Prof. Michael S. Shur, Prof. Jamal Deen, Prof. Magali Estrada, Prof. Yue Kuo, Prof. Bill Eccleston, Prof. Takao Someya, Dr. Paul Heremans, Dr. Gerwin Gelinck, Dr. Hagen Klauk, Dr. Warren Jackson (HP), Dr. Euan Smith (CDT), Dr. Erik van Veenendal (Polymer Vision), Dr. Tolos Voutsas (Sharp Labs of America),...

Papers are solicited on the following topics:
Materials for Flexible Electronics, Processing for Flexible Electronics, Device technologies, Physics and Characterization of TFTs on flexible substrates, Amorphous and polycristalline TFT, Transparent TFT, Organic and polymer TFT, OLED physics and characterization, Numerical and compact modeling of TFTs and OLEDs, TFT circuits on flexible substrates, Flexible AM-LCDs, Flexible AM-OLEDs, Flexible PVDs, Flexible large-area sensors and actuators...

The deadline for abstract submission will be December 3 2007.

ISFE is organized by the Engineering Conferences International Foundation, together with the Universitat Rovira i Virgili (the university of Tarragona, to which the Chairman, that is, myself, belongs).

The conference will be held in the Hotel Imperial Tarraco, close to the historical centre of the city of Tarragona, in Catalonia (Spain). The hotel, with a high standard of comfort and select international cuisine, is overlooking the "Balcony on the Mediterranean", which offers a wonderful view over Miracle Beach on the Mediterranean sea.

Tarragona is located in the south of Catalonia, in the northeast corner of the Iberian Peninsula.
Tarraco (the Roman name for Tarragona) was one of the most important cities in the Roman Empire. On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tàrraco a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.

Speaking about Tarraco’s climate, the famous Roman poet Virgil wrote: "The climate blends and confuses the seasons singularly, so that all the year seems an eternal spring." Thanks to its temperate climate, with an average yearly temperature of 23ºC, its clean beaches with fine and gloden sand, and its singular artistic and architectural heritage, Tarragona is one of the most important tourism hubs in Europe.

I truly encourage researchers on flexible electronics to submit abstracts to ISFE, and have good chances to get to know the most recent developments in the field, to make useful networking and also to enyoy some days in the beautiful city of Tarragona!

"Be Flexible" 2007

The 2007 "Be Flexible" Forum will be held in Munich (Germany) on December 5-6 2007 at the Hotel Le Meridien (Munich).

This Forum `be-flexible´ was created by Fraunhofer IZM-Munich to deal with the most recent research and innovations in the world of flexible electronics. It is an interesting event for exchanges of experiences of scientists, applied researchers, equipment suppliers and users in flexible electronics. It is also a good opportunity to meet people from the leading companies and suppliers.

The Forum will consist of two Workshops: Thin Semiconductor Devices (December 5) and Flexible Electronics Systems (December 6). Some interesting papers will be presented. In the area of device physics and modeling, I want to mention a paper entitled "Conduction mechanisms in conjugated polymers", by N. Sedghi, M. Raja, D. Donaghy, and W. Eccleston, from the University of Liverpool. Prof. Eccleston's team is a pioneer in the field of physics and compact modeling of organic devices.

Besides, December 7 will be an Open Day to visit the Fraunhofer IZM facilities.

Fourth Annual Printed Electronics USA

The fourth annual Printed Electronics USA symposium will be held in San Francisco, California (in the South San Francisco Conference Center), on November 12-15. This conference aims to be the largest in the World on the topic of Printed Electronics. It covers both organic and printed inorganic electronics.

The premium conference will include more than 60 presentations from users/potential users, and a very large printed electronics exhibition, with over 50 exhibitors.

This conference focuses more on the potential and applications of printed electronics rather than on the physics and modeling of the devices for printed electronics. However, no doubt it will be a very interesting conference to attend for device researchers, in order to learn more about the revolutionary applications printed electronics is going to have.

The program will also include tours to local companies as well as half day Printed Electronics Investment Summit.

Besides, the 2007 Printed Electronics Awards, for recognition of industry and technology development, will be given.

Sunday, 7 October 2007

Global Plastic Electronics Conference

The 3rd Global Plastic Electronics Conference and Showcase will be held in Frankfurt, Germany, on October 29-30 2007. The venue will be the Sheraton Frankfurt Hotels & Towers, Conference Centre.

The program consists of nine parallel symposia: Flexible Displays, Lighting & Signage, Photovoltaics, Organic Based Sensors, Organic labels & Tags, Smart Packaging, Smart Textiles, Fuel Cells & Batteries and Hybrid Opportunities.


The Global Plastic Electronics Conference and Showcase will be a very appropriate place to learn about the recent advances on plastic electronics, and also to do networking. The plenary speakers are leading authorities in the field, as well as some of the presenters.

The Call for Posters is still open! It is a good oportunity to present a scientific poster and have a chance to meet the leaders in plastic electronics.

Besides, more than 30 companies will participate in the Showcase. As said in the brochure, Science and Industry will meet in this conference.

ICCAD'07

The 2007 IEEE International Conference on Computer Aided Design (ICCAD) is coming...
It will take place in San Jose, California on November 5-8. The venue will be the Double Tree Hotel in San Jose..

ICCAD is one of the top conferences in electronic design conference. This year it will be its 25th anniversary.

The program of the 25th Edition of ICCAD is truly interesting. On Monday 5 there will be 4 half-day tutorials and 1 full-day tutorial, all of them conducted by very prestigeous researchers. The selected papers are all of high quality. ICCAD is a very competitive conference, which carries out a careful selection of the papers submitted. Less than one third of the submissions are accepted.

Besides, there are there are 4 embedded tutorials addressing topics from nano-photonic circuits over physical synthesis and formal verification to compact device modeling for 45 nm and below.

The program will also be complemented with with 2 top-notch plenary keynote speakers: Jeff Welser, Director of the SRC National Nanoelectronics Research Initiative, and John Kibarian, CEO of PDF Solutions.

Modeling is one of the topics of ICCAD. One of the embedded tutorials will address compact device modeling for 45 nm and below, and it will be presented by Kevin Cao and Colin McAndrew. But in ICCAD other modeling issues are emphasized: power modeling, reliability modeling, interconnect modeling , variability modeling, and timing modeling.

In fact, one of the tutorials is entitled Modeling Deterministic Timing and Reliability Effects in Sub-65 nm Flows, and will be conducted by S. Pullela, C. Kashyap and B. McGaughy.

Certainly ICCAD will be a very interesting place to learn and discover the latest new research developments in electronic design technology, and to exchange ideas about the challenges and solutions for the design nanoscale integrated circuits.

And Happy Birthday to ICCAD!

2008 IEEE Symposium on VLSI Technology

The 2008 IEEE Symposium on VLSI Technology will take place in the Hilton Hawaiian Village, in Honolulu, Hawaii, on June 17-19.

The IEEE Symposium on VLSI Technology is one of the most prestigeous conferences on VLSI devices and processes. It is also a very competitive and tough conference. Papers should always be innovative enough regarding VLSI devices. Some of the topics explicitly mentioned in the Call for Papers are "process/device modeling" and "theories and fundamentals" related to VLSI devices. Therefore, researchers in device modeling (including compact modeling) can submit papers to the IEEE Symposium on VLSI Technology, but it should be remarked that these models or theories should be real breakthroughs.

The Chairman is Professor Jason Woo, from UCLA, an outstanding researcher in semiconductor devices, with a lot of experience in device modeling.

The deadline is January 7.

There will be a Best Student Paper Award. The Symposium will cover the travel mexpenses and registration fee for the award recipient to attend the 2009 Symposium.

The IEEE Symposium on VLSI Technology will be held in conjunction with the IEEE Symposium on VLSI Circuits, which is one of the top conferences in the field of integrated circuits. This Symopisum is also very demanding and competitive. Papers should be really breakthroughs to be accepted.

Well, despite the symposium is so demanding, it is worthy to work hard to make a suitable paper for this Symposium. And it is also a good opportunity to enjoy some days in Honolulu!

RFIC'08

The 2008 IEEE RFIC (Radio Frequency Integrated Circuits) Symposium will be held in Atlanta, Georgia, on June 15-17 in conjunction with the IEEE MTT-S International Microwave Symposium (IMS), as part of the Microwave Week 2008.

The IEEE RFIC Symposium is one of the most important IEEE conferences dedicated to the latest innovations in RF and microwave integrated circuits.

The technical areas of RFIC 2008 include RFIC design, RFIC circuits, design methodology, system engineering, RF testing and packaging... And I wish to hightlight that one of the topics explicitly mentioned in the Call for Papers is "Modeling and CAD: RFIC Modeling, Characterization of Active and Passive Devices".

Certainly, RFIC'08, as well as IEEE MTT-S IMS, will allow an easy interaction between high-frequency compact model developers and their potential users.

The deadline for paper submission is January 3 2008.

IMS 2008

The IEEE MTT-S International Microwave Symposium 2008 (IMS 2008) will be held in Atlanta, Georgia from June 15 to June 20 2008.

IMS is the largest conference in the field of RF and microwave theory and techniques.

IMS'08 will include workshops, to be held on Sunday June 15, Monday June 16 and Friday June 20 2008. The IMS 2008 Technical Sessions will take place from Tuesday June 17 to Thursday June 18.

In such a large conference, there are many parallel sessions. The scope of IMS is large, and papers on compact modeling of semiconductor devices in the RF and microwave regime can be presented at IMS. In fact, IMS is a very adequate forum for that, because of the presence of the potential users of the device models (designers of RF and microwave circuits).

IMS will be part of the Microwave Week 2008, which will also include a microwave exhibition, the RFIC Symposium and the ARFTG Conference.

The deadline for paper submission is December 7 2007.

Last but not least, IMS'08 includes a very interesting social programme, and a guest tour roster.
Certainly Atlanta is an exciting city that offers many places and activities to enjoy!

Friday, 5 October 2007

EUROSOI'08

The 2008 EUROSOI Workshop will be held in Cork, Ireland, on January 23-25 2008.

The EUROSOI Workshop started as an event related to a former Coordination Action funded by the European Commission. EUROSOI was a Thematic Network which included most of the European teams working on SOI technology. Actually, this network will be funded again for three years more.

The EUROSOI Workshop has become an international forum to discuss the recent advances on all aspects of SOI technology: materials, devices, modeling, simulation and circuits.

EUROSOI 2008 will be organized by the Tyndall National Institute in Cork. The Chairman is Prof Jean-Pierre Colinge, a recognized pioneer in SOI technology.

The deadline for abstract submission is November 16 2007

Tuesday, 2 October 2007

European Microwave Week (EuMW) 2007

European Microwave Week provides the opportunity to attend four conferences and various workshops and short courses given by leading experts in their field. Moreover, the European Microwave Exhibition constitutes the largest trade show on RF and microwaves in Europe.

Following the pattern established in Paris in 2005, European Microwave Week now consists of four conferences:

The event focuses on the needs of engineers and researchers and seeks to serve both academia and industry. The week provides an opportunity for both communities to consider the latest trends and developments that are widening the field of application of microwaves.


European Microwave Week 2007 continues the series of successful microwave events and is set to return to Munich, Germany. By the, way, I cannot stand but recommending you to take this opportunity, and have a try with the Oktoberfest... It is actually worth it!

2008 IEEE International Reliability Physics Symposium

For over 40 years, IRPS has been the premier conference for engineers and scientists to present new and original work in the area of microelectronic device reliability. Originally started in the early 1960’s by the military and aerospace community, IRPS is now co-sponsored by the IEEE Reliability Society and the IEEE Electron Devices Society. This co-sponsored event has drawn participants from the United States, Europe, Asia and all other parts of the world. IRPS 2008 promotes the reliability and performance of integrated circuits and microelectronic assemblies through an improved understanding of failure mechanisms in the user’s environment, while demonstrating the latest state-of-the-art developments in electronic reliability.

The focus of the symposium is the 3-day plenary/parallel sessions (at the Phoenix Convention Center) featuring original work that identifies new microelectronic failure or degradation mechanisms, improves understanding of known failure mechanisms, demonstrates new or innovative analytical techniques, or demonstrates ways to build-in reliability. Specific areas to be addressed during the 2008 IRPS are reliability concerns associated with silicon (integrated circuits, discrete devices, MEMS), non-silicon (GaAs, LEDs and diode lasers, optical fiber and flat panel displays), and emerging technologies including organic electronics and nanotechnology:

  • Product Reliability and Burn-In
  • Non-Volatile Memory
  • Qualification Strategies
  • Circuits and Systems
  • Soft Error Effects
  • Assembly and Packaging
  • Failure Analysis
  • Transistors
  • High Power Devices
  • Devices and Processing
  • Interconnects
  • Device Dielectrics
  • ESD and Latch-Up
  • Process Induced Damage
  • MEMS
  • Nanoelectronics Device Reliability
  • Organic Electronics

Other opportunities at the symposium include:

  • A 2-day Tutorial Program featuring a set of bound notes from all tutorials. Attendees have the opportunity to learn a new area in some technical depth from an industry expert or brush up on the fundamentals with introductory tutorials. There are typically about 20 tutorials that are offered on topics ranging from back-end reliability to gate dielectric and transistor reliability to circuit/product reliability to assembly/ packaging reliability.
  • Reliability Year-In-Review Seminar. This seminar provides a summary of important work published from the previous year in key reliability areas. Industry experts serve as the “tour guide” and save you time by collecting and summarizing this information to bring you up to date in a particular area as efficiently as possible.
  • Evening Session Workshops enhance the synergy of the symposium by affording the attendees an opportunity to meet in informal groups to discuss key reliability physics topics with the guidance of experienced moderators. Some of the workshop topics are directly coupled to the tutorial program to allow more discussion on a particular topic.
  • Equipment Demonstrations held in parallel with tutorials and technical sessions are a unique aspect of this symposium. Manufacturers of state-of-the-art analytical and test and stress equipment are on hand to demonstrate their products and systems to individuals and small groups. Attendees are encouraged to bring samples or questions for onsite analysis and discussion.
  • An Evening Poster Session has become an important part of the IRPS for authors and attendees to discuss recent research and results in a very interactive environment.

    There are lots of opportunities to be involved in increasing your understanding of this technically important field. We look forward to seeing you in Phoenix!

Wednesday, 19 September 2007

Out-of-Topic: Smiley emoticon

It is a very out-of-topic post, but I think that it is quite important, culturally speaking. Today (September 19th, 2007), this emoticon :-) becomes 25 years old. Visit the homepage of its creator ( Scott E. Fahlman ) for more information.

Monday, 17 September 2007

ISPSD'09

The 21st IEEE International Symposium on Power Semiconductor Devices and ICs will take place in Barcelona (Catalonia, Spain) on June 14-18.

The deadline for abstract submission is October 24 2008.

ISPSD is the main international conference on the areas of power semiconductor devices, power integrated circuits, their hybrid technologies, and applications.

Topics include: processes, materials, CAD/Simulation, devices, power ICs, packaging and applications.

For researchers interested in compact modeling of power semiconductor devices, ISPSD is a top event to present and get to know the last results in this field. "Device & circuit simulation" is explicitly mentioned as one of the subtopic in the "CAD/Simulation" topic. Compact modeling fits very well this subject. And of course, there is a subtopic of "Modeling" in the "Device" topic.

The Conference will take place mainly at the Axa Winterthur Auditorium but some parallel sessions will be held at the NH Constanza Hotel which is just beside the Auditorium.

Certainly Barcelona is a wonderful place to have such an important event. There are many superb attractions in Barcelona: historical landmarks, the well-known modernistic buildings in Gaudi-style, the "Barri Gòtic" (middle-age downtown), the Museum of Fine Arts, or the stadium of the Barça Football Club. And one can find nice beaches very close to Barcelona. The weather in June is usually very good, warm enough to go to the beach, without been too hot.



The last edition of ISPSD was a success.

The 20th IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD) was held May 18–22, 2008, in Orlando, Florida, USA.

The venue of ISPSD'08 was the Windham Orlando Resort, a tropical paradise located just outside the entrance to the Walt Disney World in Orlando, Florida.


The General Program Chairman was Professor T. Paul Chow, from the Rensselaer Polytechnic Institute (RPI), in Troy NY. Prof. Chow is a recognized authority in the field of power devices and circuits.

ICCDCS'08

The 7th International Caribbean Conference on Devices, Circuits and Systems has just released the call for papers. This conference is biannually held in different locations near the Caribbean Sea, and is a very inspiring place to present new results. This edition will be held on 28-30 April, 2008, in Cancun, Quintana Roo, Mexico, which is near many interesting archaeological sites, as well as touristic resorts. If you want more information, visit their homepage, but I would not think twice about going there.... (the deadline is on January, 18, so you have plenty of time...)

Sunday, 16 September 2007

New compact modeling papers published in IEEE Transactions on Electron Devices

The September issue of IEEE Transactions on Electron Devices includes an Special Issue on Simulation and Modeling of Nanoelectronics Devices, where most papers are about numeriocal modeling and simulations.

Among the regular papers, there are many about compact modeling. It is certainly a very hot topic!

My former and excellent Ph D student Hamdy Abd El Hamid has published a great work presenting a 3D analytical model for the subthreshold swing in FinFETs. This work was done in collaboration with researchers from the SOI group at the Universite catholique de Louvain: Prof. Denis Flandre and Dr Valeria Kilchytska.

J. Deng and H-S. P. Wong present very interesting analytical models of electrostatic gate capacitance of 1-D field-effect transistors (FETs) with multiple cylindrical conducting channels. The observed agreement with 3D numerical simulations is very good. The paper also shows that effective ways to improve device speed areincreasing the number of channels per gate and reducing the gate height.

R. Kaur et al. present a unified subthreshold model for sub-100-nm nonuniformly doped channel MOSFET. The model is shown to be valid for different lateral and transverse channel-engineered structures, by comparing with 2D simulations. Based on the results obtained, the authors propose a novel device architecture incorporating the benefits of asymmetric halo and LDD doping.

W. Bian et al. present an analytic potential-based model for the undoped surrounding-gate MOSFETs. It is based on the same approach as the paper by D. Jimenez et al,as well as the one by B. Iñiguez et al. but is written on a potential-based formulation.

S. Locci et al. present an analytical model for cylindrical thin-film transistors, which was validated by comparison with experimental results. The authors also compare the performances of cylindrical TFTs with those of planar TFTs.

S. Bayshia et al. propose an analytical subthreshold surface potential model for dual-material gate MOSFETs which considers a varying depth of the channel depletion layer. Good agreement was found with 2D numerical simulations.

A. S. Roy and C. C. Enz develop an analytical large-signal cyclo-stationary low-Frequency noise with arbitrary periodic input. They show that an averaged time constant and an averaged trap density can model the cyclo-stationarity of RTS and flicker noise, respectively.

R. Grazner, F. Schwierz and V. M. Polyakov present an analytical model describing the effects of 2D quantum–mechanical carrier confinement on the threshold voltage of undoped multiple-gate MOSFETs. This model was valiudated by a comparison with self-consistent solutions of 1-D and 2-D Schroedinger and Poisson equations.

M. I. B. Shams et al. show in their paper that in a C-V model of ultrathin gate dielectric MOS devices it is necessary to include the dependence on the barrier height at the Si–dielectric interface and the substrate doping density, and they propose an empirical equation which considers these effects.

S. Kristiansson, F. Ingvarsson and K. O. Jeppsson present a compact spreading resistance model for substrate noise coupling analysis which uses no fitting parameters and is also scalable with the resistivity and thickness of the substrate, as well as with the contact size.

CMRF 2007

The 2007 Workshop on Compact Modeling for RF/Microwave Applications (CMRF'07), organized in conjunction with the IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM2007) will be held on October 3 2007 in Boston, Massachussets.

CMRF 2007 is sponsored by the Delft Institute for Micro-electronics and Submicrontechnology and technically co-sponsored by the IEEE Electron Devices Society.

CMRF is focused on the compact modeling for RF and microwave applications, but not only of bipolar devices. Papers on RF and microwave FET devices can also be presented at CMRF. In fact, CMRF has become a very useful event to get a good picture of the state-of-the-art in this field, and discuss the new trends on compact modeling for RF and microwave applications of all types of devices.

The 2007 edition of CMRF will consist on four sessions: SiGe Compact Modeling, Analog Circuit Verification, III-V compact modeling, and Advanced Characterization and Modeling for RF Power Applications.


Besides, this year CMRF will include a meeting of experts from advanced SiGe technology and from III-V technology.

BCTM'07

The 2007 IEEE Bipolar and BiCMOS Circuits and Technology Meeting (BCTM2007) will be held in Boston, Massachussets, from September 30 to October 3 2007. The conference site will be the Marriot Long Wharf Hotel in Boston.

BCTM is the largest conference in bipolar and BiCMOS technologies and circuits, addressing fabrication, design, performance, testing and applications of bipolar and BiCMOS devices and circuits.


BCTM'07 will include three modeling sessions about bipolar devices: one large signal modeling session, one session about thermal effects, modeling and reliability, and one session about bipolar modeling and characterization. The power device session also incxludes one paper about compact thermal modeling.

In conjunction with BCTM'07, there will be a number of intersting BCTM short courses.

But for compact modeling researchers, the most interesting event held in conjunction with BCTM 2007 is the Workshop on Compact Modeling for RF/Microwave Applications, on October 3 2007.

BMAS 2007

The 2007 IEEE International Behavioral Modeling and Simulation Conference (BMAS 2007) will be held in San Jose, CA, on September 20-21, in conjunction with the 2007 Custom Integrated Circuits Conference (CICC), in the Doubletree Hotel in San Jose, at the heart of Silicon Valley.

BMAS addresses behavioral modeling and simulation for analog electronic circuits and systems. Topics include the development and application of behavioral languages and simulators, modeling practices and automatic extraction of models. Particular focus is placed on the Verilog-AMS and VHDL-AMS languages are of particular interest. The General Chair is Colin C. McAndrew (from Freescale Semiconductor), a recognized authority in the field of compact and behavioral modeling.

This year the BMAS program consists of several interesting sessions: applications of behavioral modeling, behavioral modeling tools, two sessions about behavioral models, and one poster and exhibit session.

Among the models presented in BMAS 2007, we can highlight a liquid crystall cell macro-model with Verilog-A, a SPICE model for piezoelectric transducers, a MEMS accelerometer model, a phase change memory model using Verilog-A, and a behavioral simulation of biological neuron systems using VHDL and VHDL-A.

For compact and behavioral modeling researchers, BMAS is no doubt a very interesting conference to attend, and for circuit designers, it is a very good complement to CCIC.

Wednesday, 12 September 2007

Paper on de-embedding RF FETs

In this month's issue of Electronics Letters, there is a paper titled "Simplified RF noise de-embedding method for on-wafer CMOS FET", by Xiong, Y.-Z. Issaoun, A. Nan, L. Shi, J. Mouthaan, K. . I think it is interesting enough for all those of you that are using measurements.

Tuesday, 11 September 2007

November 2007 issue of IEEE Transactions on Circuits and Systems, Part-I

This issue will be a special issue on circuits and computing architectures in the emerging area of Nanotechnology. Among other, I've found some papers that I think are worth a look:

Title: Modeling of the Electrical Conductivity of DNA
Authors: Vedrana Hodzic, Vildana Hodzic, Robert W. Newcomb

As they say in the abstract: "We have developed a PSpice model of the electrical behavior of DNA molecules for use in nanoelectronic circuit design. To describe the relationship between the current through DNA and the applied voltage we used published results of the direct measurements of electrical conduction through DNA molecules. The experimental dc current-voltage (I-V) curves show a nonlinear conduction mechanism as well as the existence of a temperature dependent semiconductive voltage gap. A weighted least-squares polynomial fit to the experimental data at one temperature, with fitted temperature dependent polynomial coefficient of the linear term, was used as a mathematical model of electrical behavior of DNA. An equivalent electrical circuit was created in PSpice in which DNA was modeled as a voltage-controlled current source described by the mathematical model that includes temperature dependence, GPOLY(T) . Using this model, PSpice simulations with this model generated current-voltage-curves at other temperatures that were in excellent agreement with experimental data"


Title: CNTFET Modeling and Reconfigurable Logic Circuit Design
Authors: Ian O'Connor, Junchen Liu, Frédéric Gaffiot, Fabien Prégaldiny, Christophe Lallement, Cristell Maneux, Johnny Goguet, Sebastien Frégonèse, Thomas Zimmer, Lorena Anghel, Trinh Dang, Régis Leveugle

This paper examines aspects of design technology required to explore advanced logic circuit design using CNTFET devices. An overview of current types of CNTFETs is given and highlights the salient characteristics of each. Compact modeling issues are addressed and new models are proposed implementing (i) a physics-based calculation of energy conduction sub-band minima to allow a realistic analysis of the impact of CNT helicity and radius on the dc characteristics and (ii) descriptions of ambipolar behavior in Schottky-Barrier CNTFETs and ambivalence in double-gate CNTFETs. Using the available models, the influence of the parameters on the device characteristics were simulated and analyzed. The exploitation of properties specific to CNTFETs to build functions inaccessible to MOSFETs is also described, particularly with respect to the use of double-gate CNTFETs in fine-grain reconfigurable logic.

Paper on Science

There is a paper on this month issue of Science from some people of IBM, stating that they have "seen" the dopant distribution in a nano-scale device. The point is, leaving apart the technique, that the dopant does not get an uniform distribution, even after annealing. See the paper: Imaging of Arsenic Cottrell Atmospheres Around Silicon Defects by Three-Dimensional Atom Probe Tomography, by Keith Thompson, Philip L. Flaitz, Paul Ronsheim, David J. Larson, and Thomas F. Kelly

Monday, 10 September 2007

IEEE Trans. on Electron Devices

This month's issue is a "Special Issue on Simulation and Modeling of Nanoelectronics Devices". That means that I will not look for papers, but I'll only say that all of them are quite interesting. There are papers on threshold voltage modeling, on modeling of statistical variations, on quantum effects,... So, have a look!

Papers on the Applied Physics Letters

I've found some interesting paper on this month's issue:

Estimation of electron traps in carbon-60 field-effect transistors by a thermally stimulated current technique, by Toshinori Matsushima, Masayuki Yahiro, and Chihaya Adachi

Ballistic quantum transport in a nanoscale metal-oxide-semiconductor field effect transistor, by Vijay K. Arora, Michael L. P. Tan, Ismail Saad, and Razali Ismail

Tuning of electrical characteristics in networked carbon nanotube field-effect transistors using thiolated molecules
, by Chun Wei Lee, Keke Zhang, H. Tantang, Anup Lohani, S. G. Mhaisalkar, Lain-Jong Li, T. Nagahiro, K. Tamada, Y. Chen

These are three quite different topics, but I think that they are interesting enough.

Thursday, 6 September 2007

IEEE Awards

I've just received the list of the 2007 IEEE Awards, and I wanted to make a comment. First of all, many congratulations to dear Prof. Michael S. Shur, for his two (yes, TWO) awards. The first award is the Leon K. Kirchmayer Graduate Teaching Award, that goes to those able to show inspirational guidance of graduate students in all IEEE fields of interest. Prof. Shur obviously is a most than adequate recipient for this award. His second award (jointly with Arturas Zukauskas) is the Donald G. Fink Prize Paper Award, and goes to the authors of the most outstanding paper published by the IEEE.

I also want to congratulate Prof. Yannis P. Tsividis, who is the recipient of the 2007 Gustav Robert Kirchhoff Award, that goes to those providing outstanding contributions to the fundamentals of any aspect of electronic circuits and systems that has a long-term significance or impact. Again, Prof. Tsividis is a mythical figure in the field of Device Modeling.

In brief, many congratulations for them and for all the other recipients of the IEEE Awards!

Wednesday, 5 September 2007

Free Keithley Web Seminar on Measurement

This seminar covers precision test and measurement applications for an emerging class of low cost (<$1000 USD) 6½-digit digital multimeters. Learn how to assemble a testing error budget for various applications for electronic devices and products. Examples include simple test programming to support automatic acquisition and evaluation of measurement data, as well as basic front panel operation.

By participating in this seminar, you will learn and understand:

  • How to establish a measurement accuracy budget for an application
  • How to account for central and parasitic sources of error
  • How to match your accuracy requirements with the appropriate DMM
  • How to calculate system test uncertainties and errors

This seminar is recommended for development and test engineers and scientists who need to make high precision electrical measurements using widely available, highly accurate 6½-digit DMMs.

About the Presenter:

Chuck Cimino is the Marketing Director for Multi-Application Instruments at Keithley Instruments, Inc. in Cleveland, Ohio. He joined Keithley Instruments in 1981 and has held many positions, including Test Engineer, Design Engineer, Project Manager, and Product Marketer.
The seminar will be broadcasted over the internet and requires your registration prior to the event.

When is it?

Europe: Thursday, September 13, 2007
15:00 Central European Time
(UTC/GMT: 13:00)


To register for this FREE webcast seminar click here.

Sunday, 2 September 2007

Primer Seminario en Nanoelectrónica y Diseño Avanzado 2007

A friend of mine (Francisco J. Garcia Sanchez) has sent me the announcement of the first Seminar on Nanoelectronics and Advanced Design to be held at the INAOE in Puebla, Mexico. Here you have the link: http://www-elec.inaoep.mx/castour2007

The program is VERY interesting, with five stellar speakers, and, best of all, the admision is free...

P R O G R A M

Dr. Francisco J. Garcia Sanchez, /Universidad Simón Bolivar, Caracas, Venezuela
De la Microelectrónica a la Nanoelectrónica: Una Visión de la Evolución de los Dispositivos Electrónicos.

Prof. Krishnendu Chakrabarty, /Duke University, USA
Modular Testing of Core-Based System-on-Chip Integrated Circuits.

Prof. Rajendra Singh, /Clemson University, South Carolina, USA
Nanotechnology and Pathways to Green Energy Conversion

Prof. Naveen K. Yanduru , /Design Manager, Texas Instruments, Inc. Dallas, Tx, USA
Front-ends in deep sub-micron CMOS with an example of a WCDMA, GSM/GPRS/EDGE receiver front-end without inter-stage SAW filter in 90nm CMOS.

Dr. Mauricio Terrones, /Advanced Materials Department, IPICyT, San Luis Potosí, México.
Recent Advances on N-doped Carbon Nanotubes: Applications and Biocompatibility

For more information:
Dr. J. Alejandro Díaz
ajdiaz@inaoep.mx
Tel y Fax: (222) 2470517

Thursday, 23 August 2007

Agilent Announces New HVMOS Package For IC-CAP Software

I copy part of the press release (please note the language they use):

Agilent Technologies Inc. announced the availability of a new parameter extraction solution for high voltage (HV) complementary metal oxide semiconductor (CMOS) devices used in a range of automotive and consumer products, as well as LCD and display driver applications. The HVMOS extraction package, for use with Agilent's Integrated Circuit Characterization and Analysis Program (IC-CAP) software platform, enables engineers to model HV CMOS devices using Synopsys' HSPICE simulator, HVMOS Level 66 compact model.

Implemented as a compact model in HSPICE, HVMOS Level 66 compact model outperforms most other HVMOS model solutions in speed and convergence. The HVMOS model includes all relevant physical effects unique to high-voltage operation, including symmetric and asymmetric source and drain resistances, quasi-saturation, transconductance fall off at high-gate voltage, and self-heating effects. As a result, it allows HV CMOS devices to be modeled with unparalleled DC and capacitance modeling accuracy and simulation speed. HVMOS models are used by both analog and digital designers during circuit simulation.

Source: Semiconductor Online

Wednesday, 22 August 2007

Statistical simulation of memories

In the last issue of electronics letters (August 2 2007, vol 43, issue 16), there is an interesting paper on statistical simulation of sub-100nm memories. Here you have the link to the abstract, and try to have a look at it. I think that this (I mean: incorporating statistical techniques into the whole model) is an issue for a good compact model to be accepted by the design community.
Otherwise, if there is no way to take into account the huge variations in modern technologies, the model will be quite useless for them.

Monday, 20 August 2007

Scaling effects on short-channel organic transistors

If you are interested in organic transistors, perhaps you will appreciate having a look at the paper "Scaling effect on the operation stability of short-channel organic single-crystal transistors", appeared in the Applied Physics Letters of 6 August 2007 (link).
As they say in the abstract: "Organic single-crystal transistors allowed the authors to investigate the essential features of short-channel devices. Rubrene single-crystal transistors with channel lengths of 500 and 100 nm exhibited good field-effect characteristics under extremely low operation voltages, although space charge limited current degrades the subthreshold properties of 100 nm devices. Furthermore, bias-stress measurements revealed the remarkable stability of organic single-crystal transistors regardless of device size. The bias-stress effect was explained by the trapping of gate-induced charges into localized density of states in the single-crystal channel."

Wednesday, 25 July 2007

ISCAS'08

The 2008 IEEE International Symposium of Circuits and Systems (ISCAS 2008) will be held in Seattle (Washington, USA), on 18-21 May 2008.

ISCAS is the largest conference in the area of Circuits and Systems. It is sponsored by the IEEE Circuits and Systems Society. Prestigeous speakers in this field are always invited.

ISCAS 2008 will focus on the theme "Green Circuits and Systems: Engineering the Environmental Revolution".

The deadline for regular paper submission is October 5 2007. As indicated in the Call for Papers, the scope of ISCAS 2008 includes all topics related to integrated circuits and systems. Papers on compact modeling for circuit design are considered to address some of the topic of the call. In fact, every year a number of interesting papers on compact modeling are presented at ISCAS.

It is important to mention that in ISCAS posters are very well considered, as important as oral presentations. Many authors choose poster as their presentation format.

On the other hand, a "rich and intersting social programme is planned". It still has to be announced. Sounds promising, anyway.

New papers about compact modeling

A number of interesting papers have been published in the August issue of Transactions on Electron Devices.

In a paper entitled "Accuracy of Surface-Potential-Based Long–Wide-Channel Thick-Base MOS Transistor Models", Bin B. Jie and Chih-Tang Sah (University of Florida, Gainesville) discuss the accuracy of several surface-potential based MOSFET models. They show that the accuracy of the approximations done in these models is not so good in the accumulation and subthreshold regimes, and they propose a new analytical model showing better accuracy in those regimes.

Ananda S. Roy, Christian C. Enz and J. -M. Sallese, researchers from the EKV team at EPFL (Lausanne, Switzerland) present an analytical noise modeling paradingm for lateral nonuniform MOSFETs. They show that in these devices the bias dependence of the noise parameters cannot be predicted by conventional Klaassen-Prins (KP)-based methods.

Modeling of irradiated devices is always a hot topic. H. T. Mebrahtu et al. present SPICE models of Fluorine-Ion irradiated CMOS devices, using the EKV MOSFET model as a basis.

In this issue we also find new modeling work on Double-Gate MOSFETs. Researchers from the University of Thessaloniki (Greece) and MINATEC (Grenoble, France) have presented a paper entitled "Semi-Analytical Modeling of Short-Channel Effects in Si and Ge Symmetrical Double-Gate MOSFETs". The doping is considered in this work. The analysis is carried out in the subthershold regime, and the mobile charge is assumed to be negligible compared to the doping charge. The model shows that Ge Double-Gate MOSFETs are more prone to short-channel effects than Si Double-Gate MOSFETs.

Finally, B. Bindu, N. DasGupta and A. DasGupta (Indian Institute of Technology, Madras) present "A Unified Model for Gate Capacitance–Voltage Characteristics and Extraction of Parameters of Si/SiGe Heterostructure pMOSFETs". This analytical model is physically-based, and shows very good agreement with experimental measurements.