Wednesday, 18 October 2017

#opensource Summit Europe 2017 https://t.co/c1TgRIgzVE https://t.co/RZqPRisbbS


from Twitter https://twitter.com/wladek60

October 18, 2017 at 11:41PM
via IFTTT

Tuesday, 17 October 2017

A Compact QS Terminal Charge and Drain Current #Model for DG Junctionless Transistors and Its Circuit Validation https://t.co/hTsw5blL8f


from Twitter https://twitter.com/wladek60

October 17, 2017 at 11:26AM
via IFTTT

[paper] Accurate diode behavioral model with reverse recovery

Stanislav Banáša,b, Jan Divínab, Josef Dobešb, Václav Paňkoa
aON Semiconductor, SCG Czech Design Center, Department of Design System Technology, 1. maje 2594, 756 61 Roznov pod Radhostem, Czech Republic
bCzech Technical University in Prague, Faculty of Electrical Engineering, Department of Radioelectronics, Technicka 2, 166 27 Prague 6, Czech Republic
Volume 139, January 2018, Pages 31–38

Highlights:

  • The complex robust time and area scalable Verilog-A model of diode containing reverse recovery effect has been developed.
  • Due to implemented reverse recovery effect the model is useful especially for high-speed or high-voltage power devices.
  • The model can be used as stand-alone 2-terminal diode or as a parasitic p-n junction of more complex lumped macro-model.
  • Two methods of model parameter extraction or model validation have been demonstrated.

ABSTRACT: This paper deals with the comprehensive behavioral model of p-n junction diode containing reverse recovery effect, applicable to all standard SPICE simulators supporting Verilog-A language. The model has been successfully used in several production designs, which require its full complexity, robustness and set of tuning parameters comparable with standard compact SPICE diode model. The model is like standard compact model scalable with area and temperature and can be used as a stand-alone diode or as a part of more complex device macro-model, e.g. LDMOS, JFET, bipolar transistor. The paper briefly presents the state of the art followed by the chapter describing the model development and achieved solutions. During precise model verification some of them were found non-robust or poorly converging and replaced by more robust solutions, demonstrated in the paper. The measurement results of different technologies and different devices compared with a simulation using the new behavioral model are presented as the model validation. The comparison of model validation in time and frequency domains demonstrates that the implemented reverse recovery effect with correctly extracted parameters improves the model simulation results not only in switching from ON to OFF state, which is often published, but also its impedance/admittance frequency dependency in GHz range. Finally the model parameter extraction and the comparison with SPICE compact models containing reverse recovery effect is presented [read more...]

FIG: Solving the recursive calculation of reverse recovery charge

Sunday, 15 October 2017

Software #model multi-level #photonic #IC designs https://t.co/24rtqqVTBH


from Twitter https://twitter.com/wladek60

October 15, 2017 at 01:05AM
via IFTTT

Thursday, 12 October 2017

5 #benefits of contributing to #opensource projects https://t.co/qKsBgkR9Uh


from Twitter https://twitter.com/wladek60

October 12, 2017 at 09:30AM
via IFTTT

Monday, 9 October 2017

Intern/Student in SW Eng. for Power Management f/m

Job Description: You will be responsible for developing a SW tool enabling an user friendly and efficient framework to program system-on-chip. The flexibility of our power management solution thanks to enhanced customization is indeed a critical asset requiring a reliable tool from programming definition to release. You will be part of an enthusiastic and international system engineering team located in Munich and will get in touch locally with several design and validation teams [read more...]

Your main tasks in this full time position min 5 months up to 12 months will be to:

  • Create several functions/add-ons enhancing entry interface
  • Develop a compiler to better explore new chip architectures-Integrate compiler output with existing tools
  • Implement sanity checkers detecting
  • Develop test scenarios and requirements for chip validation
  • Contribute to the reporting and documentation for other teams and management

Saturday, 7 October 2017

#Linux Now Has its First #OpenSource #RISC-V Processor https://t.co/cdM2NNXBoE


from Twitter https://twitter.com/wladek60

October 07, 2017 at 11:33PM
via IFTTT