Sunday, April 22, 2018

Performance Potential of #Ge #CMOS Technology From a Material-Device-Circuit Perspective https://t.co/cSWOhx5xSn #paper


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April 22, 2018 at 03:19PM
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Subthreshold Modeling of TriGate Junctionless Transistors With Variable Channel Edges & Substrate Bias Effects https://t.co/ZScVIyoP3k #paper https://t.co/ZScVIyoP3k


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April 22, 2018 at 03:03PM
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Subthreshold Modeling of TriGate Junctionless Transistors With Variable Channel Edges & Substrate Bias Effects https://t.co/ZScVIyoP3k #paper


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April 22, 2018 at 03:03PM
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Compact Drain Current #Model for #TFT Under Bias Stress Condition https://t.co/t8RWZbee7Z


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April 22, 2018 at 03:31PM
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Friday, April 20, 2018

[Extended Deadline] Special IEEE TED Issue on “Compact Modeling for Circuit Design"

Call for papers for 
Special IEEE TED Issue
on
Compact Modeling for Circuit Design

Extended deadline: May 15, 2018               Publication date: January 2019

In order to capture the full potential of semiconductor devices, compact device models and design software are critically needed. Predictive and physical device and circuit design software are required to accelerate development cycles and tackle issues of device efficiency, manufacturing yield and product stability. The performance/accuracy of the design software is dependent on the availability of accurate device models, and for circuit design, compact models.

In particular, compact device models are the vehicle that allows the design of circuits using the targeted devices. The compact model should not only accurately capture the physics of the device in all operation regimes, but at the same time should also have an analytical or semi-analytical formulation to be used in automated design tools for the simulation of circuits containing several or many devices. On the other hand, compact models can also be used as a tool to make clear estimations and predictions of the performances of future devices following technological trends. The lack of adequate compact models for a number of emerging devices is mostly due to the insufficient understanding of the physical mechanisms that govern their behaviours. Regarding many emerging non-silicon structures, devices, circuit and system designers very often rely on empirical behavioural macro-models and/or use existing silicon device compact models based on the conventional understanding of transport processes. However, for these emerging non-silicon devices, neither approach provides a fully adequate device description under all operation conditions, nor the quantitative predictive quality required for the accurate production quality design.

Therefore, the main objective of this dedicated special issue is to engage Electron Devices Community in a serious discussion with their scholarly contributions specifically focused on solving major challenges in the broad area of compact device modeling for circuit design.

Suggested topics include but not limited to:
  1. Silicon MOSFET modeling: Advanced Bulk MOSFETs; SOl MOSFETs; Multi-Gate MOSFETs: Double-Gate MOSFETs, Surrounding-Gate MOSFETs, FinFETs, UTB SOI MOSFETs; Junctionless MuGFETs; Power and High Voltage MOSFETs.
  2. Junction-based and compound semiconductor FET modeling: Advanced MESFETs; Advanced HEMTs; lIl-V and Ill-N; MOSFETs; Advanced IFETs.
  3. Diode and bipolar transistor modeling: Advanced BJTs; HBTs; IGBTs; pn and pin diodes; Varactors.
  4. Emerging transistor modeling: Tunnel FETs; Molecular transistors; Single Electron Transistors; Quantum Dot Transistors; Negative Capacitance Transistors.
  5. Emerging semiconductor devices: Memories, MRAM, PCRAM etc.; Spintronic devices; Layered/2D materials
  6. Thin-Film FETS (TFT): a-Si:H TFTs; Polycrystalline Si TFTs; OTFTs and OECTs; Oxide TFTs; Single-crystal TFTs.
  7. Modeling of physical effects: Noise; High frequency operation; Mismatch; Strain; High energy particle interactions in ICs (Cosmic rays and energy beams); ESD events; Ballistic and quasi-ballistic transport; Layout dependent effects.
  8. Photonic devices: LEDs and OLEDs; Photodiodes; Solar cells; Photodetectors; SPADs.
  9. Model implementation in EDA tools and applications: Model code adaptation to EDA tools; Computational model performances in design tools; Challenges of model implementation in design tools; Compact model applications to variation and statistical analysis; Compact model applications to thermal analysis; Compact model applications to design exploration; Compact model applications to design optimization; Compact model applications to device process improvements; Compact modeling for BSD prediction; Circuit design using new compact models.
Submission instructions: Manuscripts should he submitted in a double column format using an IEEE style file Please visit the following link to download the templates:
http://www,ieeeiorg/publicationsistandards/publications/authors/author7templates,html
In your cover letter, please indicate that your submission is for this special issue. Please submit papers using the website: http://mc.manuscriDtcentral.com/ted

Guest Editors:
  1. Benjamin Iniguez, URV, Tarragona (SP) Editor-in-Chief
  2. Yogesh Chauhan, IIT Kanpur (IN)
  3. Andries Scholten, NXP Semiconductors, Eindhoven (NL)
  4. Ananda Roy, Intel Corporation, Portland, OR (USA)
  5. Slobodan Mijalkovic, Silvaco Europe Ltd, St. Ives (UK)
  6. Sadayuki Yoshitomi, Toshiba Corporation, Tokyo (J)
  7. Kejun Xia, NXP Semiconductors, Phoenix, AZ (USA)
  8. Wladek Grabinski, GMC Consulting, Commugny (CH)
  9. Kaikai Xu, UEST of China, Chengdu (CN) 

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Direct Measurement of Active Near-Interface Traps in the Strong-Accumulation Region of 4H- #SiC #MOS Capacitors https://t.co/e0jNWoZfQn #paper https://t.co/e0jNWoZfQn


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April 20, 2018 at 08:15PM
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Direct Measurement of Active Near-Interface Traps in the Strong-Accumulation Region of 4H- #SiC #MOS Capacitors https://t.co/e0jNWoZfQn #paper


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April 20, 2018 at 08:14PM
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